tag: 65nm

Fabless Approach To Embed Active Nanophotonics in Bulk CMOS By Co-Designing The BEOL Layers For Optical Functionality (MIT)
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “Metal-Optic Nanophotonic Modulators in Standard CMOS Technology” was published by researchers at Massachusetts Institute of Technology. Abstract: "Integrating nanophotonics with electronics promises revolutionary applications ranging from light detection and ranging (LiDAR) to holographic displays. Although semiconductor manufacturing of nanophotonics in Silicon ... » read more

Pandemics And Panic Chip Buying
By Mark LaPedus - 18 Jun, 2020 - Comments: 0

U.S.-China trade tensions are creating uncertainty in the semiconductor market, but it is also causing another event right now—panic chip buying. At present, some but not all foundry vendors are seeing “rush orders” for select products and are running their fabs at full capacity. It’s not just leading-edge devices, but also mature technologies. A surge of chip orders started in Ma... » read more

Insider’s Guide To Photomasks
By Mark LaPedus - 17 Mar, 2016 - Comments: 1

Semiconductor Engineering sat down to talk about photomasks and lithography with Franklin Kalk, executive vice president of technology at Toppan Photomasks, a merchant photomask supplier. What follows are excerpts of that conversation. SE: What’s hot in mask technology these days? Kalk: It’s everything from the bleeding-edge like EUV to much more mature manufacturing. On the mature si... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Will Wearables Work Well Enough?
By Ed Sperling - 02 Apr, 2015 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler The rollout of the Apple Watch later this month has reset expectations for the wearable electronics market, just as early implementations of the Pebble, Fitbit and Google Glass helped raise awareness about a new level of portability and connectivity. Early projections are for strong sales, which in turn will propel a new level of connectedness for the ... » read more

Drowning In Data
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

Leveraging The Past
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

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