tag: AMD

A Broad Look Inside Advanced Packaging
By Mark LaPedus - 18 Nov, 2021 - Comments: 0

Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion. SE: Where are we in the semiconductor cycle right now? Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 12 Nov, 2021 - Comments: 0

Chipmakers AMD has rolled out its new MI200 series products, the first exascale-class GPU accelerators. Using a fan-out bridge packaging technology, the MI200 series are designed for high-performance computing (HPC) and artificial intelligence (AI) applications. The MI200 series accelerators feature a multi-die GPU architecture with 128GB of HBM2e memory. Typically, the HBM2e memory stack a... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 29 Oct, 2021 - Comments: 0

Chipmakers After years in the works, GlobalFoundries is finally a public company. But on its first day of trading on Thursday (Oct. 28), shares of the foundry vendor slipped a bit. GF finished its first day of trading at $46.40. This compares to the $47 per share it priced in the initial public offering (IPO), according a report to Reuters. The chipmaker has a market capitalization of about $2... » read more

Scaling Bump Pitches In Advanced Packaging
By Mark LaPedus - 25 Oct, 2021 - Comments: 0

Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them. The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as d... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 17 Sep, 2021 - Comments: 0

Automotive Arm announced a new software architecture, two reference hardware implementations, and its role leading a new industry group that will work on open-source software for automotive use. The Scalable Open Architecture for Embedded Edge (SOAFEE) is based on Arm’s Project Cassini and SystemReady, aims to help the automotive industry move to software-defined systems by tackling the comp... » read more

System-In-Package Thrives In The Shadows
By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Sep, 2021 - Comments: 0

Tools & IP Cadence and Samsung Foundry are offering Mixed-Signal OpenAccess-ready process design kit (PDK) technology files that support a range of Samsung process technologies from 28FDS to GAA base 3nm. Enabling access to mixed-signal designs in a common OpenAccess database, the co-design methodology promotes shared responsibilities and collaboration between the analog and digital teams ... » read more

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