Material Effects: Trading Performance For Power


By Ann Steffora Mutschler Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon ge... » read more

Bridging IP With Verification Standards


By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

Storm Before The Calm


The announcements out of ARM and Intel over the past couple week—and presumably from rivals AMD, MIPS and even Nvidia in coming weeks—are more than just a struggle for one-upmanship. The goal is much more far-reaching and the stakes are significantly higher than who has the fastest processor or core or even the lowest-power version. In the past year there has been a massive push to expan... » read more

Betting On 3D


The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Power Or Performance?


By Pallab Chatterjee Most microprocessors have shifted to new small geometry processes in order to be the most efficient at power and high performance. However there is always a trade-off between power, performance and area (PPA) for semiconductors, and this is especially relevant for processors. In the current design space, processors are created as general-purpose products, but they are gene... » read more

The Power Of 3D


By Cheryl Ajluni Much to the dismay of anyone who recently splurged on a new Blu-ray disk player or flat-panel HDTV, 3D stereoscopic content has become the talk of the town or, in this case, the 2010 Consumer Electronics Show. Sure, we’ve been down this road before. After all, 3D is nothing new. But it now appears ready to explode into the home in the form of 3D television (Figure 1). Bol... » read more

Low-Power Architectures Go Mainstream


By Pallab Chatterjee Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology. There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions fr... » read more

Why Intel Is Settling With AMD


There’s more to the Intel-AMD settlement than meets the eye. While Intel will be paying out $1.2 billion to AMD as part of the settlement—and that’s a large chunk of money in anyone’s book—it’s a relatively small price to pay when it’s amortized over 10 years and can open the door to even bigger markets for Intel. And that’s just what this is, a down payment on the future. ... » read more

Outsourcing’s New Face


By Ed Sperling As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties. Outsourcing is hardly new concept in business. In the early pa... » read more

Moore’s Law vs. Low Power


By Ed Sperling Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together. The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take... » read more

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