tag: ARM

HW-Enabled Security Techniques To Improve Platform Security And Data Protection For Cloud Data Centers And Edge Computing (NIST)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A technical paper titled "Hardware-Enabled Security: Enabling a Layered Approach to Platform Security for Cloud and Edge Computing Use Cases" was published by NIST, Intel, AMD, Arm, IBM, Cisco and Scarfone Cybersecurity. Abstract: "In today’s cloud data centers and edge computing, attack surfaces have shifted and, in some cases, significantly increased. At the same time, hacking has becom... » read more

Cybersecurity Risks Of Automotive OTA
By John Koon - 01 Dec, 2022 - Comments: 0

Modern vehicles increasingly resemble supercomputers on wheels, with many electronic control units (ECUs) networked together as increasingly sophisticated software is installed and updated. Similar to smartphones, vehicle OEMs will contact vehicle owners remotely about operating system updates that add new features and/or fixes, as well as software bugs and vulnerabilities. But all of this h... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2022 - Comments: 0

Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Blog Review: Nov. 23
By Jesse Allen - 23 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at multiple data points to get a sense of effort spent in FPGA verification and increasing demand for FPGA verification engineers. Synopsys' Rimpy Chugh, Himanshu Kathuria, and Rohit Kumar Ohlayan argue that the quality of the design and testbench code is critical to a project’s success and that linting offers a comprehensive checking process for teams to s... » read more

Chip Industry’s Technical Paper Roundup: Nov. 21
By Linda Christensen - 21 Nov, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=65 /] » read more

Week In Review: Design, Low Power
By Marie C. Baca - 18 Nov, 2022 - Comments: 0

Tools and IP Cadence announced that its IP for GDDR6 is now silicon-proven for TSMC’s N5 process technology. The IP consists of Cadence PHY,  controller design IP, and verification IP (VIP), and is targeted for very high-bandwidth memory applications. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 fami... » read more

Profile-Guided HW/SW Mechanism To Efficiently Reduce Branch Mispredictions In Data Center Applications (Best Paper Award)
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications" was published by researchers at University of Michigan, ARM, University of California, Santa Cruz, and Texas A&M University. This work was awarded a best paper award at October's 2022 Institute of Electrical and Electronics Engineers (IEEE)/Association for Computing Machin... » read more

Challenges In Backside Power Delivery
By Laura Peters - 17 Nov, 2022 - Comments: 0

One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm
By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

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