Blog Review: Nov. 13

By Jesse Allen - 13 Nov, 2019 - Comments: 0

Applied Materials' Buvna Ayyagari-Sangamalli argues that the siloed structure that produced the computing eras of the past will not be sufficient to fuel the AI era and that a new codesign approach to everything from architecture to materials is needed. Arm's Wendy Elsasser examines emerging non-volatile memories and how they have triggered innovation for new memory protocols and optimized s... » read more

Revving Up For Edge Computing

By Ed Sperling - 07 Nov, 2019 - Comments: 1

The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

Blog Review: Nov. 6

By Jesse Allen - 06 Nov, 2019 - Comments: 0

Cadence's Paul McLellan considers why high-performance compute, high-performance networks, and security will all be vital to the next wave of devices and the importance of optimization. Synopsys' Taylor Armerding points to some best practices for assessing your supply chain to find the weak links that could lead to a security breach, from why to make it a priority to what to ask software ven... » read more

Service Revenue Growing With Chip Complexity

By Ann Mutschler - 04 Nov, 2019 - Comments: 0

Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

Blog Review: Oct. 30

By Jesse Allen - 30 Oct, 2019 - Comments: 0

Cadence's Paul McLellan checks out the future of the automotive industry, the options for making the transition to autonomous driving, and how experience with electric vehicles influences perception of them. In a video, Mentor's Colin Walls digs into the challenges of testing memory in an embedded system. A Synopsys writer looks at doubling bandwidth in PCIe 5.0, the PHY logical changes a... » read more

Rapid Evolution For Verification Plans

By Brian Bailey - 28 Oct, 2019 - Comments: 0

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Week In Review: Design, Low Power

By Jesse Allen - 25 Oct, 2019 - Comments: 0

ANSYS will acquire Dynardo, a provider of simulation process integration and design optimization (PIDO) technology. Dynardo's tools include algorithms for optimization, uncertainty quantification, robustness, scenario variation, sensitivity analysis, simulation workflow building and data mining. Based in Weimar, Germany, Dynardo was founded in 2001 and has been an ANSYS software partner; the ac... » read more

Utilizing Computational Memory

By Brian Bailey - 24 Oct, 2019 - Comments: 0

For systems to become faster and consume less power, they must stop wasting the power required to move data around and start adding processing near memory. This approach has been proven, and products are entering the marketplace designed to fill a number of roles. Processing near memory, also known as computational memory, has been hiding in the shadows for more than a decade. Ever since the... » read more

RISC-V Challenges And Opportunities

By Ed Sperling - 24 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Blog Review: Oct. 23

By Jesse Allen - 23 Oct, 2019 - Comments: 0

ANSYS' Magdy Abadir digs into the challenges associated with identifying and modeling electromagnetic crosstalk and the architectural and design trends that contribute to it. Cadence's Paul McLellan listens in as automotive security expert Charlie Miller points to how close we are to Level 4 autonomy and where in a car attack surfaces lie. Mentor's Brent Klingforth checks out the process ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?