tag: ASIC

5 Best Practices For Successfully Managing An ASIC Supply Chain
By DELTA, a part of FORCE Technology - 05 Nov, 2018 - Comments: 0

Managing an end-to-end ASIC supply chain is one of the primary challenges of chip projects. Not only is the process long and complex, but it involves multiple technologies, dependencies and stakeholders. In this paper, we've assembled five best practices to help you translate ASIC specifications into a final product through a smooth supply chain process, including: Avoid costly time-... » read more

Reduction In First Silicon Success
By Brian Bailey - 25 Oct, 2018 - Comments: 0

Every two years, Harry Foster, chief scientist for Mentor, a Siemens Business, works with Wilson Research to do a verification study. Those studies have influenced many in the industry, indicating where users are experiencing the most pain, spending their time, growing their team sizes and where money would be best spent. However, over the past four years, the ASIC industry has basically been i... » read more

Using ASICs For AI Inferencing
By Ed Sperling - 10 Oct, 2018 - Comments: 0

Flex Logix’s Cheng Wang looks at why ASICs are the best way to improve performance and optimize power and area for inferencing, and how to add flexibility into those designs to deal with constantly changing algorithms and data sets. https://youtu.be/XMHr7sz9JWQ » read more

Using High-Bandwidth Memory
By Ed Sperling - 01 Oct, 2018 - Comments: 0

eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

Achieving ASIC Timing Closure With Speedcore eFPGAs
By Achronix - 05 Sep, 2018 - Comments: 0

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is ... » read more

Adding NoCs To FPGA SoCs
By Ann Mutschler - 28 Jun, 2018 - Comments: 0

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and de... » read more

FinFET ASICs: It Takes A Platform
By Mike Gianfagna - 28 Jun, 2018 - Comments: 0

Sophisticated, specialized ASIC technology is making an impact on the everyday world around us. Whether it’s a gadget you can have a conversation with, a car that will take over driving from time to time, or internet speeds that seem impossibly fast, there is likely sophisticated custom silicon present as a critical enabling technology. Plenty has been written about advanced ASICs for network... » read more

FPGAs Becoming More SoC-Like
By Ann Mutschler - 04 Jun, 2018 - Comments: 1

FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This family of devices now includes everything from basic programmable logic all the way up to complex SoC devices.... » read more

Inside UVM, Take Three
By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

In-Design Rail Analysis Is A Beautiful Thing
By Kenneth Chang - 22 Mar, 2018 - Comments: 0

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

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