Cadence Janus NoC System IP


The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

Easing EV Range Anxiety Through Faster Charging


The automotive industry is developing new ways to boost the range of electric vehicles and the speed at which they are charged, overcoming buyer hesitation that has limited the total percentage of EVs to 18% of vehicles being sold.[1] Work is underway to improve how batteries are engineered and manufactured, and how they are managed while they are in use or being charged. This extends well b... » read more

Blog Review: July 10


Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Chip Industry Week In Review


Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

Navigating Chiplet-Based Automotive Electronics Design With Advanced Tools And Flows


In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive secto... » read more

Thermal Challenges Multiply In Automotive, Embedded Devices


Embedding chips into stacked-die assemblies is creating thermal dissipation challenges that can reduce the reliability and lifespan of these devices, a growing problem as chipmakers begin cramming chiplets into advanced packages with thinner substrates between them. In the past, nearly all of these complex designs were used in tightly controlled environments, such as a large data center, whe... » read more

Verification Tools Straining To Keep Up


Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Chip Industry Week In Review


The Design Automation Conference morphed into the Chips to Systems Conference, reflecting an industry shift from monolithic SoCs to assemblies of chiplets in various flavors of advanced packaging. The change drew a slew of students and a resurgent buzz, fueled by discussions about heterogeneous integration, reliability, and ways to leverage AI/ML to speed up design and verification processes. ... » read more

Navigating The Future Of EDA


The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not just reshaping how we approach design and verification in electronics; they are redefining the possibilities within the field. Our latest podcast episode delved deep into this topic, uncovering t... » read more

Digital Twins Gaining Traction In Complex Designs


The integration of heterogeneous chiplets into an advanced package, coupled with the increasing digitalization of multiple industry segments, is pushing digital twins to the forefront of design. The challenge in these complex assemblies is figuring out the potential tradeoffs between different chiplets, different assembly approaches, and to be able to do it quickly enough to still hit market... » read more

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