tag: chip design

Identifying Sources Of Silent Data Corruption
By Laura Peters - 08 May, 2025 - Comments: 0

Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets. ... » read more

Digital Twins For Design And Verification Workflows
By Brian Bailey - 27 Mar, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior d... » read more

What’s Missing From Predictions
By Brian Bailey - 30 Jan, 2025 - Comments: 1

At this point everyone has made their predictions for the year, but there is one thing many people get wrong. Predictions are not about innovation. They are about pain and what is causing it. This industry is risk-averse, and everyone wants to continue doing what they are doing. But there comes a point when it's so painful to continue that something has to change. Having something that is... » read more

2025: So Many Possibilities
By Brian Bailey - 16 Jan, 2025 - Comments: 0

The stage is set for a year of innovation in the chip industry, unlike anything seen for decades, but what makes this period of advancement truly unique is the need to focus on physics and real design skills. Planar scaling of SoCs enabled design and verification tools and methodologies to mature on a relatively linear path, but the last few years have created an environment for more radical... » read more

Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation" was published by researchers at NVIDIA Research. Abstract: "Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, ... » read more

Design And Verification Issues In 2024
By Brian Bailey - 19 Dec, 2024 - Comments: 0

At the end of each year, I look back over the stories published and those that top the charts in terms of readership. I concentrate on those stories that are about the EDA tools and flows and the factors that are influencing them. These are good indicators of the problems designers and verification teams are facing today, and where they are looking for answers. This year's leading categories... » read more

Goal-Driven AI
By Brian Bailey - 26 Nov, 2024 - Comments: 2

For many, the long-term dream for AI within EDA is the ability to define a set of goals and tell the computer to go design it for them. A short while later, an optimized design will pop out. All of today's EDA tools will remain hidden, if they even exist at all. You would only be limited by your imagination. But we also know that AI is not to be trusted today, especially when millions of dol... » read more

AI-Powered Data Analytics To Revolutionize The Semiconductor Industry
By Reela Samuel - 30 May, 2024 - Comments: 1

In the age where data reigns supreme, the semiconductor industry stands on the cusp of revolutionary change, redefining complexity and productivity through a lens crafted by artificial intelligence (AI). The intersection of AI and the semiconductor industry is not merely an emerging trend—it is the fulcrum upon which the next generation of technological innovation balances. Semiconductor comp... » read more

Advanced Design Planning In IC Compiler II
By Synopsys - 28 Feb, 2024 - Comments: 0

By Rajiv Dave, CAE Manager, Synopsys. Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning: Capacity to handle the largest design optimally yet ... » read more

Chip Industry Silos Are Crimping Advances
By Brian Bailey - 11 Jan, 2024 - Comments: 0

Change is never easy, but it is more difficult when it involves organizational restructuring. The pace of such restructuring has been increasing over the past decade, and often it is more difficult to incorporate than technological advancements. This is due to the siloed nature of the semiconductor industry, both within the industry itself, and its relationship to surrounding industries. Inc... » read more

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