Chiplet Placer with Thermal Consideration for 2.5D ICs


A new technical paper titled "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration" was published by researchers at National Yang Ming Chiao Tung University (Taiwan). Abstract "This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning... » read more

How To Build Resilience Into Chips


Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Keysight Acquires Cliosoft


Keysight announced today that it has acquired Cliosoft, adding IP data management and design data to its EDA portfolio. The deal comes at a time when chip designs are becoming more heterogeneous and customized, making it more difficult to keep track of a growing number of IP assets. What works for one market or sub-market may not be optimal for another. That could include everything from di... » read more

Will AI Take My Job?


Everyone is talking about ChatGPT these days, and I am sure we will be comparing it with Google's new offering before long. I thought it was time that I gave it a quick spin, and since I am preparing to moderate a webinar about chiplets as I write this, I decided it was a good example of a fairly new field and would be a good test. I started by asking, "What are semiconductor chiplets, what ... » read more

Taming Corner Explosion In Complex Chips


There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

How To Make Chiplets A Viable Market


At the recent Chiplet Summit, there was a panel session on the last afternoon titled "How to Make Chiplets a Viable Market." The panel was moderated by Meta's Ravi Agarwal, and the panelists were (from left to right in the photo): Travis Lanier of Ventana Micro Systems...actually Travis couldn't make it and Ventana was represented by Charles, but I didn't catch his last name Clint Walk... » read more

Dealing With Performance Bottlenecks In SoCs


A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Chiplets Taking Root As Silicon-Proven Hard IP


Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics


Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Research Bits: Feb. 6


Pillars for chiplet integration Researchers from the Tokyo Institute of Technology proposed a new chiplet integration technology called Pillar-Suspended Bridge (PSB), which they say is a simpler method of chip-to-chip connection compared to silicon interposers and redistribution layers. In the PSB, only a pillar-shaped metal structure called a "MicroPillar" is interposed at the connection b... » read more

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