tag: chiplets

Securing Heterogeneous Integration at the Chiplet, Interposer, and System-In-Package Levels (FICS-University of Florida)
By Technical Paper Link - 04 Aug, 2022 - Comments: 0

A new research paper titled "ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance" was published by researchers at the Florida Institute for Cybersecurity (FICS) Research, University of Florida. Abstract "The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Pa... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 29 Jul, 2022 - Comments: 1

The U.S. Congress approved the CHIPS Act, a mammoth bipartisan achievement the New York Times called “the most significant government intervention in industrial policy in decades.” As passed, the full package — now called the Chips and Science Act — contains $52 billion in direct assistance for the semiconductor industry, along with $24 billion in tax incentives. In addition, the bill c... » read more

Distilling The Essence Of Four DAC Keynotes
By Brian Bailey - 28 Jul, 2022 - Comments: 0

Chip design and verification are facing a growing number of challenges. How they will be solved — particularly with the addition of machine learning — is a major question for the EDA industry, and it was a common theme among four keynote speakers at this month's Design Automation Conference. DAC has returned as a live event, and this year's keynotes involved the leaders of a systems comp... » read more

Heterogenous Integration Creating New IP Opportunities
By Brian Bailey - 19 Jul, 2022 - Comments: 0

The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble, because there will be many potential standards introduced, and they are likely to change quickly as the industry explores what is r... » read more

Customization, Heterogenous Integration, And Brute Force Verification
By Ed Sperling - 14 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

What Future Processors Will Look Like
By Ed Sperling - 13 Jul, 2022 - Comments: 0

Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

Delay-based PUF for Chiplets to Verify System Integrity
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs" by researchers at University of Massachusetts, Amherst MA, Abstract (partial): "In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure un... » read more

Security Risks Widen With Commercial Chiplets
By Ed Sperling - 07 Jul, 2022 - Comments: 0

The commercialization of chiplets is expected to increase the number and breadth of attack surfaces in electronic systems, making it harder to keep track of all the hardened IP jammed into a package and to verify its authenticity and robustness against hackers. Until now this has been largely a non-issue, because the only companies using chiplets today — AMD, Intel, and Marvell — interna... » read more

EDA Gaps At The Leading Edge
By Ed Sperling - 29 Jun, 2022 - Comments: 1

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

Week In Review: Manufacturing, Test
By Ed Sperling - 17 Jun, 2022 - Comments: 0

Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more

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