tag: coverage

Abstract Verification
By Brian Bailey - 24 Oct, 2019 - Comments: 1

Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become an accepted and trusted methodology. This becomes particularly true when we bring abstraction into the picture. A virtual prototype is meant to be true to behavior, but there could be timing d... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs
By Madhur Bhargava - 10 Oct, 2019 - Comments: 0

By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

Disregard Safety And Security At Your Own Peril
By Brian Bailey - 10 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2019 - Comments: 0

Mentor's Neil Johnson argues that coverage closure shouldn't have to be mad scramble in the home stretch of development if designers change their early development mindset. In a video, Cadence's Amol Borkar explains Simultaneous Localization and Mapping, or SLAM, from the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Synopsys' Tay... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Next-Generation Vehicles Pose Automotive Semiconductor Test Challenges
By Advantest - 07 May, 2019 - Comments: 0

Various market trends are driving requirements for automotive semiconductor test as technology increasingly defines the future of the automobile. According to IHS Markit, the total market for semiconductors, having reached nearly $500 billion in 2018, will grow at a CAGR of 4.88% through 2022, while the automotive electronics category, reaching more than $40 billion in 2018, will outpace the to... » read more

Verification At 7/5nm
By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

The Role Of EDA In AI
By Brian Bailey - 17 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Safety Critical Design In Automotive
By Ed Sperling - 03 Apr, 2019 - Comments: 0

Shiv Chonnad, hardware engineer at Synopsys, examines how to design chips for safety-critical applications such as automotive and ensure they work as planned and in accordance with ISO 26262 and the various ASIL levels. This includes how to find faults at both a chip and a system level. https://youtu.be/3dL4ZuSe5Ls » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

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