1xnm DRAM Challenges


At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Memory Lane: Far From A Leisurely Stroll


The only semiconductor market segment that has not been taken over by the foundries and still remains dominated by IDMs is the memory sector. The memory market is the last bastion for true IDM manufacturers, who must be savvy in the changing trends in end market applications, advanced technology development, and must still determine how much and when to invest in additional capacity. With on... » read more

An Insider’s Guide To Planar And 3D DRAM


Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

Will 3D-IC Work?


Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

Optimizing LPDDR4 Performance And Power With Multi-Channel Architectures


PDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper explains how LPDDR4 is different from all previous JEDEC... » read more

Executive Insight: Sehat Sutardja


Sehat Sutardja, chairman and CEO of Marvell, sat down with Semiconductor Engineering to talk about new approaches for design and memory and why costs and time to market are forcing changes in Moore's Law. What follows are excerpts of that conversation. SE: What was behind your move into modular packaging? Sutardja: The cost of building chips is getting out of hand. As we make things more ... » read more

Changes In Chip Design


We all know that sub-10nm is coming. But is that really what will define the next generation of semiconductors? Progress in semiconductor technology increasingly is not just about advancements in the hardware. It also involves advancements in applications and technologies peripheral to the devices themselves. That may sound counterintuitive, but going forward the technology, applications and... » read more

The Week In Review: Manufacturing


South Korea’s SK Hynix led the initial charge in the development of High Bandwidth Memory (HBM), a 3D DRAM technology based on a memory stack and through-silicon vias (TSVs). SK Hynix has been shipping HBM parts in the market. Now, SK Hynix and Samsung are readying the next version of the technology, dubbed High Bandwidth Memory 2 or HMB2, according to a report from The Electronic Times of So... » read more

Rethinking Memory


Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

Manufacturing Bits: Dec. 15


DRAM scaling sans EUV At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was believed that DRAMs would hit the wall and stop scaling at 20nm or so. Then, at that point, the industry would need to migrate to a 3D DRAM structure or a next-generatio... » read more

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