tag: Dennard’s Law

Homogeneous And Heterogeneous Computing Collide
By Brian Bailey - 22 Nov, 2016 - Comments: 0

Eleven years ago processors stopped scaling due to diminishing returns and the breakdown of [getkc id="213" kc_name="Dennard's Law"]. That set in motion a chain of events from which the industry has still not fully recovered. The transition to homogeneous multi-core processing presented the software side with a problem that they did not know how to solve, namely how to optimize the usage of ... » read more

Moore’s Law Debate Continues
By Ann Mutschler - 02 Nov, 2016 - Comments: 0

Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

No More Straight Lines
By Ed Sperling - 12 May, 2016 - Comments: 0

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

FinFET Scaling Reaches Thermal Limit
By Brian Bailey - 12 May, 2016 - Comments: 2

In 1974, Robert H. Dennard was working as an IBM researcher. He introduced the idea that MOSFETs would continue to work as voltage-controlled switches in conjunction with shrinking features, providing doping levels, the chip's geometry, and voltages are scaled along with those size reductions. This became known as Dennard's Law even though, just like Moore's Law, it was anything but a law. T... » read more

Industry Road Map Under Construction
By Ed Sperling - 21 Jan, 2016 - Comments: 0

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

Darker Silicon
By Katherine Derbyshire - 29 Jan, 2015 - Comments: 0

For the last several decades, integrated circuit manufacturers have focused their efforts on [getkc id="74" comment="Moore's Law"], increasing transistor density at constant cost. For much of that time, Dennard’s Law also held: As the dimensions of a device go down, so does power consumption. Smaller transistors ran faster, used less power, and cost less. As most readers already know, howe... » read more

More Problems Ahead
By Ed Sperling - 14 Aug, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: We’re starting to hear talk about octuple patterning. We’ve ... » read more

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