More Problems Ahead

Experts at the table, part 1: Patterning, feature shrinks and voltage scaling are all making it more difficult to keep pace with Moore’s Law.

popularity

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries.

SE: We’re starting to hear talk about octuple patterning. We’ve got persistent problems with EUV. We’ve got new materials because electrons can’t move through existing ones at 10nm. What do you see as the biggest challenges ahead.

Liebmann: The biggest challenge is that there is no one biggest challenge. Leading up to these advanced nodes, in what we now reflect upon as the ‘good old days,’ everything was driven by dimensional scaling. We had one major problem to solve, which was to reduce the pitch, reduce feature sizes, shorten channel lengths, shorten wires, increasing density—all of that made Moore’s Law possible. It all went back to how we make things smaller and denser. It was very much driven by lithography—how do we get better lithography? And ultimately that was driven by reducing wavelengths, increasing numerical apertures. We worked very closely with the lithography tools suppliers. That was the main focus, and everything else fell into place. What we’re seeing now is that if you reduce feature sizes, your leakage goes up with the transistor, your wiring resistance goes through the roof, your capacitance increases and performance suffers. At some point if you’re doing too many exposures to get one level done it’s not cost-effective anymore. It’s like squeezing a balloon. You can solve any one problem at a time, but when you do something else pops up.

Brand: There are three major problems we’re facing. One is particularly bad because we don’t have a solution. Clearly, patterning below the 20nm pitch will be quite difficult with double and quadruple patterning, and maybe there will be the need to combine quad patterning plus complicated-cut masks. Another is how to make the device work at very small feature sizes. Just like the patterning, there are workarounds for that. The third issue is how to do the voltage scaling of the transistor. That’s one we can live without to some extent, even though there will be a big compromise on power. But the ability to continue to reduce voltage is something that is almost without a solution at this point.

Banna: As we scale devices, one innovation per node is not enough. We have to schedule multiple innovations per node. That means you have to do the R&D up front, and understand what innovation works at a given node in terms of time and cost. Scheduling that is one of the biggest challenges. If you look beyond 14nm at 10nm and 7nm, people are questioning whether silicon is the right material because its carrier mobility has limits. New materials have their own challenges. Whenever we add more innovation, it drives up the cost. At the same time, the industry wants lower cost. Scheduling multiple innovations adds cost, and scaling according to Moore’s Law results in smaller and smaller spaces. Even to fit in the right device materials brings a reliability issue. You have to schedule innovation, you have to drive down the cost, and you have to meet reliability.

Arabi: We all talk about Moore’s Law stalling, but we have never moved to technology faster than today. We paused longer at 90nm, then we moved quickly to 65, 40 and 28 and then 14. So our move to technology used to be every two years, then it went to 18 months, and now it’s every 12 months. Moore’s Law is not stalling. It’s actually going faster. But the problem is the economy of Moore’s Law. We used to integrate more and it cost less, which created this huge opportunity for chipmakers to push the boundaries of imagination in coming up with bigger CPUs, GPUs, DSPs and all this interesting functionality, and offering it at the same price or even cheaper to our customers. That was great. It created this cycle of innovation and product innovation. We still have the same push, which is why we are going to new processes even faster. The problem is the scale of economy is not there. It’s even more expensive. That’s the problem. We can scale it, but it’s not getting cheaper as it used to do.

SE: We’ve been running at the same trajectory of patterning, process and device innovation since about 1965 with Moore’s Law. We’re now at a point where things are obviously changing. What has to happen on the EDA side?

Banna: Technology scaling is changing the way you draw, the way you characterize what you draw, and the way you construct device functionality from what you draw. They all are interconnected. It’s not just that you’ve found the device model and you can draw and the foundries can manufacture it. From the customer side, early engagement is the only way to do the design and meet the timing schedule and meet the performance and power goals. From the EDA side, whenever there is innovation it’s going to disrupt how your tools work. You need to factor in coloring with double patterning, for example. How do the tools handle the coloring so there is no color conflict? Do you allow stitching or no stitching? Designers need to understand the impact of doing it one way versus another way. EDA, as well as the customers, have to interact with the foundries and have that learning up-front. That’s the one way forward.

Liebmann: Every node has several very fundamental new components to it. All of these components have some impact on design and require innovation in the design infrastructure. This is something we’ve overlooked for a couple nodes. For many generations we were talking about alternating phase shift, which had very significant implications on the design flow. The tools ignored this and ultimately alternating phase shift died, at least for most of us. For the larger market it never came to fruition because we didn’t think through all the design implications. The promise of high-mobility materials is not going to change the design space. But everything else, finFETs, local interconnects, different wiring optimizations for resistance and capacitance—all of that has a very profound design impact. We need to engage with the EDA community much earlier so that when we have a process solution, we also have a design solution that will work.

SE: We’ve been talking about the death of Moore’s Law since before we reached 1 micron. But what do we actually get from a shrink going forward, and when do we stop seeing enough advantage for enough companies to make it worthwhile to move ahead?

Arabi: Moore’s Law can easily go down to a couple of nanometers, but at what cost? Designs are more interconnect dominated, and the interconnect is even more important than the transistor node itself. That’s why EUV and multiple patterning are so important. You have to keep making the interconnect shorter. Moore’s Law is a self-fulfilling prophecy. It was a goal the industry set for itself based upon some empirical truth, and then we all rallied around it to make it happen—all the way from equipment makers to fabs to semiconductor companies. It became the benchmark to compete. That’s a combination of the design node technology innovation and EDA innovation. It has been easier to fulfill our goal using fab innovation, which is why we relied more on technology nodes to get our area, power and cost savings. It becomes more difficult. As we scale down in technology nodes, people will start innovating more on the architecture, EDA and circuit size until we get through some of these innovation cycles. Then we can scale down in more efficient ways. One of the reasons technology scaling is not as efficient is because we accelerated. The industry doesn’t even have time to do the proper R&D for the next technology node. Every year we are going to a new technology node. At some point you need to rely on architecture, EDA and circuit innovation to keep this trend going until we catch up on the fab size. But the return on fab and technology node scaling is not as promising right now.

Banna: Traditionally Moore’s Law gives you scaling of channel lengths and channel widths. But is that all Moore’s Law offers? With innovation, Moore’s Law can be extended further. Proponents say this. They have been introducing innovations at 90nm, 65nm, and 40nm. With the finFET, you can say the device is so strong that you don’t need nine tracks. You can do it in eight tracks or 7.5 tracks with similar or better performance. That means device innovation has contributed to Moore’s Law scaling. Going forward, we have to look at this holistically, not just local optimization. How much channel length have you scaled down or how much of the device have you scaled down. Overall, your circuit is scaling. But is it the silicon scaling or some kind of new device innovation bringing that scaling to fruition? That’s what we have to look at as an industry.

Liebmann: With no disrespect to Gordon Moore, at the core of this Moore’s Law is a really bad law. From an economic standpoint, to offer your customers twice the computing power every two years at fixed cost is not sustainable. It’s a bad economic platform. In hindsight, maybe we as an industry should have reacted to that. We’re finally at the point where we have to take action and make sure that the value of twice as many transistors is really recognized and we as an industry get our fair share of the value that’s being added to the overall economy. Things like Instagram would not be possible without the hard work of everyone in this room.

Brand: It’s good to cite the 2X rule, but the important aspect is that there needs to be continuous improvements in this technology. You want to have something that motivates people to come back and buy a new version of your product. Whether that’s 2X or a different number, the good news is that we still have an opportunity for the next few years. There’s a pretty clear path to the 7nm or 5nm node on how we’ll build the transistor and do the patterning. That’s probably as good a horizon we’ve ever had in the industry. But one thing that only comes out of the scaling of the transistor, whether it’s making the gate length shorter or the device width smaller, is the power reduction. We really can’t keep innovating in the product scale without that power reduction, which comes from the transistors. It’s right to say there are other bottlenecks, but without the intrinsic capacitance reduction in the transistor it’s hard to see how this technology can continue to improve.

Liebmann: The 2X rule will give you twice the transistor density every two years. It just might not come at fixed cost. There are some very pessimistic outlooks for cost. We’re not quite there yet. We’ll continue to see an improvement in cost per function and cost per transistor, but that is going to slow down. And along with Moore’s Law you have to observe Dennard’s Law. You can’t just scale laterally. You have to voltage, oxides and all of those things, or you run into a power problem.

To view part 2 of this discussion, click here.
To view part 3, click here.



  • Byungchun Yang

    Hi All,

    You are talking like we can shrink CDs endlessly. I wish so, too. But, I would say even 14nm node is not going to happen soon as Intel’s delay is proving. This is because BEOL portion is meeting its ending point. Via diameter of 26nm, line CD of 26nm, increased crosstalk due to overly populated lines and other features are driving IC performance and yield and thus cost catastrophically ruined. Nothing good is happening with further miniaturization to 14nm node! Why do we have to shrink CDs any further when no performance gain or cost reduction by yield increase is expected?

  • Dr. D. Gupta

    Instead of beating our chests endlessly about the slow down of Moore’s Law, let us be realistic about the very different world today and formulate :

    Moore’s 2 nd Law : Instead of the no. of transistors doubling every 2 years, these days it is the no. of Fabless companies that double every year !

    A few comments to support above :

    1. Much of the perceived delay these days in getting to HVM at new nodes is due to ever faster product cycles in the consumer electronics business, which unlike in the past is now driving the leading edge of Fab nodes.

    2. Moore’s Law should be modified for the brave new world of ever – multiplying number of immature Fabless customers who depend on lower cost Foundries w/o adequate strength or depth in Physics to efficiently integrate the many changes reqd for ea. new node.

    3. This is supported by the comment from QCOMM, the transition time from one node to the next lower has actually dropped from classical Moore’s Law 2 years to as short as 1 year. The boom in handheld which requires SoCs is the driver for the hustle. Competition among immature Fabless customers is forcing Foundries to scramble. The result is longer time to reach high yield at the new node after the lead customer gets their chips and then an even longer lifecycle for the latest node to finally cater to the stragglers and newcomers in the Fabless world, to wit 28 nm.

    4. Does IBM Micro Electronics still have any credibility in prolonging / commenting on Moore’s Law ? Have n’t they already given up on Si at 28 nm planar and decided to invest in R&D for non Si devices ?

  • Byungchun Yang

    Hi Dr. D. Gupta,
    If you are saying that we need to widen the application area of our IC device technologies (which means more Fabless companies), rather than hurrying to go to 10nm, 7nm or even 5nm node, I definitely agree with you.