More Problems Ahead

Experts at the table, part 2: How much of the future is riding on EUV; more restrictive design rules ahead, no matter what; plus, the impact of new materials.

popularity

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries.

SE: There seems to be some debate in this group about whether we’re speeding up or slowing down Moore’s Law. Which is it?

Arabi: If you take a look at TSMC’s road map, it has accelerated over the past five to six years. If you look at 20nm, we ramped up faster than 28nm, and 28nm ramped faster than 45nm. The cadence accelerated. People already are designing 14nm and 16nm even though we were working on 20nm recently. It became much more complicated because in the past it was just shrinking. Now you have to deal with materials and transistor architectures. From now on is anyone’s guess, but over the past five to six years it did accelerate.

SE: 20nm didn’t quite work as planned, which is why we saw an acceleration of finFETs. But regardless, there are more things to worry about at each node. Where are we with lithography?

Liebmann: EUV is going to come to life any day now. We’re really down to weeks rather than years. We’re very optimistic EUV will play an important role at 7nm. By our roadmap definition, that’s two nodes past this 14nm point. We’re planning to avoid quadruple patterning with single exposed EUV. It’s not entirely an economic argument. EUV is tremendously complicated and not all that cheap at this point. We need to get the volume up to get the price down. But I would not want to have a meeting with Qualcomm to explain design restrictions to make self-aligned quadruple patterning work. We need to keep wavelength-based scaling alive. Otherwise design restrictions become intolerable. Eventually we’ll have to cross that threshold, but we’re optimistic EUV will be available for the 7nm node.

Banna: We all highly desire EUV to be available today, but the fact is that the number of wafers it can process so that it is economical for the foundries is not there. The throughput level is what is stopping it. Today it’s not economical, but we’re all working hard and adding a lot of innovation, which will make it happen. When? It’s hard to say.

Liebmann: I’m optimistic. Tools have been installed. Masks have been ordered. We just need someone to flick the switch on the light source and see some photons go through there. But it’s any day now At least this year we will find out whether EUV is a reality or whether we need to look at DSA and other higher-order frequency multiplication techniques like self-aligned quadruple or octuple patterning. This is going to be the decisive year to understand the future of EUV.

Brand: Even with EUV—and we’re hoping it shows up because it will be very helpful to have a fundamental improvement to the wavelength for patterning—at 7nm that requires double patterning with EUV. And the next node will require double or quad patterning with EUV. The patterning is definitely going to be dependent on multiplication techniques. It brings in a lot of other factors, and the industry is working hard to enable the precision and spacer depositions like ALD and precise etch and characterizing many different layers in the process that become very important in terms of meeting the overlay requirements that will be necessary when you do multi-patterning. We’re characterizing many different process steps that play a role in strain fields and shrinkage on the wafer that all play into the overlay. It’s an area that requires a lot of different contributions and collaboration from the whole industry, particularly when you look at what’s going to be needed at 5nm and beyond.

Liebmann: I would gladly have the meeting at Qualcomm to explain to them the design rules to do self-aligned quadruple patterning. We can even extend that to self-aligned octuple patterning. You’re making parallel lines. We can do that. But explain how to do first metal with self-aligned quadruple patterning. That’s a very different story. It would be a fundamental change in cell architectures and design innovation at a very fundamental level. Eventually we’ll have to get there, but we’ve been trying to put that off for as long as possible. It’s not going to be well received.

Arabi: We have the advantage of not having to solve these things ourselves, but we worry about it because it drives our business equation. Double patterning has been very painful for us. It changes the way we do timing and design layouts. We had to work really hard with fabs and EDA enablers, and it’s one of those things that is so hard it changes your assumptions about many things. But once it’s done, it’s done. There is no additional investment. That’s largely behind us. But EUV is easier. We really hope it becomes available at 7nm. There are still throughput issues and cost issues, but you don’t have to apply it to all of your metals. It will probably be used for metal one, with the rest using double or triple patterning. It will co-exist for a time, even if EUV becomes viable.

SE: Assuming that EUV does become viable, does that improve the flexibility in design and reduce the number of design rules, or are we headed to more design rules anyway?

Arabi: Every node, we have more design rules. It’s a reality we’re dealing with. It would be great if we could go to a technology that simplifies our design rules, corners, DRCs and DFM. The number is exploding. Clearly we would like to do something about it, and that’s why we like EUV. It has the promise of simplifying things, but unfortunately I don’t see double and triple patterning disappearing. It will co-exist even with EUV.

Liebmann: With 14nm, wiring pitches are 64nm. Two nodes later, we should be at 32nm. That would be a good target—0.7 times 0.7. So if you look at the 32nm wiring pitch, the smallest we can expose with 193nm optical lithography solution is 80nm. So you do that twice and you get to 40. Double patterning is not going to get you to a 32nm pitch. We would be looking at something other than double patterning. This gets back to the rate of innovation. You may be comfortable with double patterning and you have design flows and EDA tools, but now we have to do more at the next node. It’s a big burden. EUV, because it is roughly 10 years late, will come in right at the resolution limit. A 32nm pitch is where we can make unidirectional gratings. It’s a very tough challenge. For cost and throughput reasons, we’re trying to come in with double patterning, but it will be a very restrictive design environment. Even if we get EUV up and running, and leaving behind all the issues of finFETs, which are very restrictive, and non-lithography things, we’re never going back to half-micron days. It’s going to get more restrictive at every node.

SE: We’ve now gotten to the point where electrons don’t move through existing materials at the same speed. Where are we with new materials, are they more difficult to work with, and what will that do to the cost?

Brand: One of the key changes in the device is coming from the electrostatic control, which is how well the gate couples into the channel and how well it turns the channel on and off. That’s the reason we’ve gone from planar devices to finFETs, and it’s reasonably predictable that if we’re going to keep scaling down the gate length will have to go to a gate-all-around structure. For that part, there are reasonably good prospects because we have good capabilities in epitaxial growth where we can put different materials onto the wafer—for example, silicon and silicon germanium have been well mastered. Then you can combine that with selective etching to remove unwanted portions of the material. So you can create a very complicated structure that would be most useful in a horizontally oriented gate-all-around structure. Another approach that could be taken is vertically grown devices where you might etch holes into a dielectric-like silicon dioxide, and then you can use epi to grow material up. Those processes are pretty well defined for certain material systems. But how good are we at bringing in completely new materials? The verdict is still out. When you look at III-V materials, can that be done? That’s something the industry is still developing. There are a lot of additional process steps that have to be developed, like creating the right dielectric and how to do the doping. Whether there’s an inflection coming soon to a new channel material is still an open question. But we have a pretty good horizon to build devices out of silicon and silicon germanium for the next couple nodes.

Liebmann: Let’s say we can build these devices. How do we wire them together? The wires are going to be 16nm wide. Most of that will be taken up by the liners that don’t conduct any current. I don’t understand the physics of this. I don’t understand how we’re going to wire up these gate-all-around structures we’re going to build. And I don’t see any materials innovation at the wiring level.

Brand: The most likely scenario is that we stay with horizontally oriented device channels. Then you can stack up the channels and get better density of current drives. Saying that requires solving some complicated etch problems, but it’s a good pathway to making this transistor density better. But you bring up a good point about the interconnect and contact scaling. It’s the liners that have to be improved. There are solutions on the table to thin down the liners, and in some cases to eliminate the liners. When you look at processes like copper and tungsten, there have to be barriers or liners put in the trenches, and there are some good ideas being put on the table to improve that to scale it down, so there will at least be a few more nodes of improvement. There are not materials more conductive than copper, but there are materials with a lower electron free pass than copper. Tungsten, nickel and cobalt have a lower electron free pass, so we can choose to make extremely limited conductors out of those other materials and they’ll scale by a factor of two better than copper. There’s a crossover in the conductance of those materials at very small feature sizes compared to copper. A tradeoff can be made on whether you want to focus on high current carrying capabilities for power distribution, or very small wires if you’re concerned about capacitance the ability to carry current over short distances. This ties into the question of overall scaling. How long do wires have to be? If can keep scaling the transistors down productively and reduce the wire length, it solves some of the problem.

To view part 1 of this discussion, click here.
To view part 3, click here.