More Problems Ahead

Experts at the table: Real costs for moving to the next nodes and what issues still need to be solved to continue shrinking features. Last of three parts.


Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries.

SE: Where are the most severe issues these days? Is it on the design side, on the manufacturing, or both?

Banna: It’s a holistic problem. We cannot pound on just the device to deliver performance node after node without considering back-end-of-line RC effects. Both have to be managed. As we scale further, the device and the back end play an important role. There are new methods to improve the resistivity of materials. But all these things need to be considered. At the same time, devices need to do their part. The way we draw circuits also needs to comprehend these limitations. I have a high-powered devices with a highly resistive back end. How do I merge these two and still get performance and power? We have to shrink the interconnect length between two metal layers and more quickly be able to go up into different metals. Maybe we have to relax the area constraints. These are the things the designers on the EDA part need to chip in so we can collectively solve these issues as an industry. They’re all interrelated.

Arabi: There are really good ideas for transistor scaling, especially around 7nm and 5nm, so we see 5nm looking really good with silicon germanium channels. There are really good ideas out there. There are nanowires. We have a lot of good ideas around transistor scaling, but it’s really the interconnect that worries me. Power density is going up and how you’re going to power them and make something useful out of them is a concern. People talk about graphene and other technologies, but those are way out there. The problem with those technologies is that they have good mobility, but to design anything you need bandgap. People forget about that. If you want to improve bandgap you have to add a lot of other things, which really degrades mobility to the point where it’s not useful anymore. So we’ll probably stay with CMOS. We may go to all-around gate and maybe nanowire and different channels, but it will still be CMOS-like. The challenge will be that we will still call them CMOS, but they will not operate completely like CMOS. Modeling them and understanding them will be an issue. So will yield, because now you are using more exotic materials. There are good ideas out there, but there is still a lot of risk.

SE: How much will it cost to develop tools on this, both within the fabs and within EDA? And will there be sufficient return?

Banna: A fab at a new node costs about $6 billion. But what I keep hearing is this: ‘We want to have a good French restaurant, so we say we will build it, but the customer wants it to serve Kung-Pao chicken.’ Customers demand high-end technologies. Recovering that cost is the driver for that. If I can’t recover the cost, there is no business there. That is the key. Whenever I build a new fab I want to make sure it is profitable. Out of the $6 billion, most of the cost is the tools—the etchers, the deposition tools, metrology.

Arabi: From the semiconductor house, going to a new technology node these days, including the entire enablement of the first device—depending on how you count, it’s between $1 billion to $2 billion. Going to a new node is not a simple decision. And it’s trending toward the higher side of that number.

SE: 28nm has been described as a long node. What does that mean for all of these advances?

Arabi: We call 28nm the technology before the cliff. It’s after 28nm that we started worrying about multipatterning and all of those interesting issues. So 28nm seems to be one of those technologies that is here to stay for a long time. I believe there will be a lot of cost optimization at 28nm. People like us will go as fast as we can to 14nm, 10nm and beyond, but there will be products that stay at 28nm. From this point forward, it won’t be a situation where the whole industry moves as a batch to the next node—especially with new product lines like wearable and IoT and 3D that don’t need advanced nodes but may eventually drive huge volume. Some of these technology nodes will be improved and still be cheaper, while advanced nodes will continue but will be more expensive. Clearly we’ll come back and make some of these technology nodes cheaper and more efficient.

Banna: 2.5D and 3D is another way to leverage existing technologies using heterogeneous integration, taking the strength of analog at 40nm or higher and the logic from 28nm and combine them together. Also, the shift that is coming up in the industry is the IoT. That is focusing on the more mature nodes. At this point it is 28nm and 40nm, but in the future it may be 14nm. That gives enough margin to the foundries because they’re all depreciated to reduce the burden of developing new technology.

Liebmann: Did you say you invest $2 billion in new nodes?

Arabi: Total design enablement and the first product, yes.

Liebmann: The EDA industry has missed a great opportunity here. If you look at how much money the end user spends on EUV before ever seeing a product show up on their doorstep—investing just on speculation of ASML eventually turning out a tool—that’s an enormous amount of money. If EDA would require investment in next-generation validation and to build a case that’s what necessary to keep moving the industry forward, well maybe it has to come to that. The foundries may have to start investing in the design more heavily because it’s such a critical part of the overall solution.

Brand: There is a tremendous investment across the industry. At Applied Materials we spend about $1 billion a year on R&D for next-generation technology, so it is substantial. We do that because there’s great complexity, and ultimately the way it’s delivered is that we address all the problems and can ramp each node at good yield. That’s the determining factor. As long as we can do the scaling and deliver more transistors per square centimeter, and as long as all the products are working through the process line to then deliver good yield, it’s a good outcome on cost. We need collaboration through the process and across the ecosystem to make sure problems are solved and processes run smoothly.

Banna: Cost is important. That’s always there. But the scaling is what has driven us to absorb that cost. As long as we continue to make the scaling and have the right innovation with optimum cost, we will be able to survive in this industry.

To view part 2 of this discussion, click here.
To view part 1, click here.

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