Creating IP In The Shadow Of ISO 26262

By Karen Heyman - 03 Aug, 2023 - Comments: 0

On many levels, designing IP for the automotive sector is similar to targeting aerospace or medical devices — human lives are at risk if something goes wrong, and the list of regulations is significant. In practice, it can turn an interesting chip design project into a complex and often frustrating checklist exercise. In the case of ISO 26262, that includes a 12-part standard for automotiv... » read more

Design IP

By Cadence - 01 Mar, 2023 - Comments: 0

Cadence is a leader in semiconductor IP addressing hyperscale computing, enterprise, data center, automotive, and artificial intelligence/machine learning (AI/ML) applications. Our IP are available in advanced-process nodes ranging from 28nm to 3nm—all silicon verified in leading-edge foundry processes. Our memory IP portfolio spans DDR, LPDDR, and GDDR. The Cadence® IP family for PCI Expres... » read more

Enablers And Barriers For Connecting Diverse Data

By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification

By Cadence - 09 Jun, 2021 - Comments: 0

We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 30 Aug, 2013 - Comments: 0

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 22 Aug, 2013 - Comments: 0

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: design IP

Creating IP In The Shadow Of ISO 26262

Design IP

Enablers And Barriers For Connecting Diverse Data

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification

Experts At The Table: Next-Generation IP Landscape

Experts At The Table: Next-Generation IP Landscape

Experts At The Table: Next-Generation IP Landscape