tag: EUV

Transistor Options Narrow For 7nm
By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

Executive Insight: Elmar Platzgummer
By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss photomask and lithography trends with Elmar Platzgummer, chief executive of IMS Nanofabrication, an Austrian-based supplier of multi-beam e-beam tools for mask writing applications. SE: IMS has shipped the world’s first multi-beam e-beam system. Initially targeted for photomask writing, the tools are currently being tested in the field. How lon... » read more

Why Is My Device Better Than Yours?
By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

EUV Still Matters…But Less
By Ed Sperling - 16 Oct, 2014 - Comments: 0

For all the chatter and occasional tirades about EUV missing its market window—it's true, EUV will have missed five market windows by 10nm—it still matters. And the sooner EUV hits the market with a viable power source, the better off the entire semiconductor manufacturing industry will be. But even EUV is a sideshow to some important shifts underway in technology. While technologically ... » read more

Litho Options Sparse After 10nm
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

Challenges Mount For EUV Masks
By Mark LaPedus - 16 Oct, 2014 - Comments: 2

Five years ago, Intel urged the industry to invest millions of dollars in the photomask infrastructure to help enable extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. At the time, there were noticeable gaps in EUV, namely defect-free masks and inspection tools. To date, however, Intel’s call to action has produced mixed results. The photomask industry is making progr... » read more

Executive Insight: Aki Fujimura
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss photomask technology and lithography trends with Aki Fujimura, chairman and chief executive of D2S. SE: What are the big challenges that keep you awake at night? Fujimura: Mask technology, and the investments in the mask industry, are increasingly important. But so far, the investment dollars that the community is willing to spend on it isn’... » read more

Executive Insight: Lip-Bu Tan
By Ed Sperling - 22 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11693" comment="Lip-Bu Tan"], president and CEO of [getentity id="22032" e_name ="Cadence"], to discuss his outlook on EDA, Moore’s Law and his strategy for investing in startups around the world. What follows are excerpts of that conversation. SE: What’s worrying you these days? Tan: There are a couple of things. One is the complex... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

One-On-One: Mark Bohr
By Mark LaPedus - 18 Sep, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel. SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process? Bohr: It’s our second-generation, tri-gate technology. So it has al... » read more

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