Week In Review: Manufacturing, Test

By Mark LaPedus - 07 Sep, 2018 - Comments: 0

Packaging Brewer Science has introduced the latest additions to its family of temporary bonding materials. The company also rolled out its new line of thin spin-on packaging materials. The company’s temporary bonding materials are called BrewerBOND. The new products, called the BrewerBOND T1100 and BrewerBOND C1300 series, are combine to create a dual-layer system for temporary bonding a... » read more

Mixed Outlook For Semi Biz

By Mark LaPedus - 25 Jul, 2018 - Comments: 0

Both the IC and fab equipment industries have been enjoying a boom cycle for some time, but they could be facing speed bumps and possibly turbulence in the second half of this year and into 2019. In the first half of 2018, the industry was fueled by the momentum carried over from 2017. DRAM prices remained relatively high, which contributed to the revenue growth in the overall IC industry. M... » read more

Bridges Vs. Interposers

By Mark LaPedus - 12 Jul, 2018 - Comments: 4

The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

MIS Packaging Takes Off

By Mark LaPedus - 07 May, 2018 - Comments: 0

Momentum is building for IC packages based on an emerging technology called molded interconnect substrate (MIS). ASE, Carsem, JCET/STATS ChipPAC, Unisem and others are developing IC packages based on MIS substrate technology, which is ramping up in the analog, power IC and even the cryptocurrency markets. MIS starts with a specialized substrate material for select IC packages. The MIS sub... » read more

Choosing The Right Interconnect

By Ed Sperling - 09 Apr, 2018 - Comments: 3

Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

FD-SOI Adoption Expands

By Ed Sperling - 21 Feb, 2018 - Comments: 2

Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

5 Takeaways From ISS 2018

By Mark LaPedus - 15 Feb, 2018 - Comments: 0

At the recent Industry Strategy Symposium (ISS) in Half Moon Bay, Calif., there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs and equipment. As part of the program, ISS also discussed the latest business and technology trends. In no particular order, here are my five takeaways from ISS: Ranging forecasts ... » read more

What’s In The Package?

By Ed Sperling - 05 Feb, 2018 - Comments: 0

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

Packaging Challenges For 2018

By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Outs vs. TSVs

By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

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