5 Takeaways From ISS 2018

Fake nodes, fan-out and robocars were addressed at the event.


At the recent Industry Strategy Symposium (ISS) in Half Moon Bay, Calif., there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs and equipment. As part of the program, ISS also discussed the latest business and technology trends.

In no particular order, here are my five takeaways from ISS:

Ranging forecasts
What’s the outlook for the IC market in 2018? Right now, there is no consensus among the analysts. Some see zero growth, while one predicts a repeat of 2017. Most are in the middle.

At ISS, Daniel Niles, founder and portfolio manager at AlphaOne NexGen Technology Fund, was bearish. In 2017, semiconductor sales were on track for 21% growth and 15% unit growth, “but end markets are not that strong with inventory building at the customer level,” according to Niles’ slide presentation at ISS.

As a result, AlphaOne predicts that the IC industry will see 0% growth in terms of sales in 2018. IC unit growth is expected to grow by 6%, but average selling prices (ASPs) will fall by 6%, according to the firm. “Major semiconductor customers have very high inventory year-over-year and so does their supply chain,” according to AlphaOne.

Then, at a separate event, Bill McClean, president of IC Insights, was more upbeat with a forecast that reflects the consensus. In total, the IC market is expected to reach $393.9 billion in 2018, up 8.3% over 2017, according to IC Insights. IC unit growth is projected to increase 11%, but ASPs could fall by 2%, according to the firm.

Malcolm Penn, chief executive of Future Horizons, is the most bullish. In 2018, Penn sees the IC market reaching nearly $500 billion, up 21.1% over 2017. The analyst says the super-cycle will continue barring a major economic disaster.

Call me a robotaxi
At ISS, Maarten Sierhuis, director of Nissan Research Center Silicon Valley, gave a presentation on autonomous driving technology. Nissan is working with NASA in the arena. GM, Tesla, Toyota and others are working on the technology.

The move to self-driving vehicles will result in major changes over the next decade, as reported in a recent article from Ed Sperling, editor in chief of Semiconductor Engineering.

In the article, Sierhuis said the shift towards autonomous driving will take place in two steps: “Eyes on, hands free, will happen in 2020 in cities. Eyes off, robotaxis, will show up in 202x. But we need to develop a system that is accessible to the way we drive. People behave differently in different places. In Amsterdam, bicycles rule. In San Francisco, pedestrians rule. And cars need to know the difference.”

Robotaxi technology is gaining steam. Self-driving taxi services combine ridesharing and autonomous vehicles. Various companies have undergone road tests in 2017 with plans to launch their commercial self-driving taxi services in 2021, according to TrendForce, which estimates the CAGR of self-driving taxis to reach 81% from 2018 to 2023.

I myself am a bit of a skeptic on the technology. But one executive told me that self-driving cars is happening faster in Europe and other regions. The U.S. is spinning its wheels with regulations and liability concerns, according to the executive.

(Source: TrendForce)

Demystifying fan-out
The world of IC packaging is an important but confusing business. Over the years, the industry has developed a plethora of different package types with an assortment of acronyms.

Why so many? Packaging is somewhat of a custom business. Customers also want a package that optimizes the performance of the chip. And that’s why packaging is key. But there is no one package type that can meet all needs. Simple chips require commodity packages. The most complex chips require advanced packages. And then there are a bunch of packaging requirements in between.

Each packaging type also has its own variations. At ISS, for example, John Hunt, senior director of engineering at Advanced Semiconductor Engineering (ASE), demystified the confusing world of wafer-level fan-out packaging. “Fan-out is not the package for every application. There is a certain sweet spot for it. It gives you the advantages you need. It’s one of our platforms. We have many others,” Hunt said in an interview after the presentation.

“Think of fan-out as more of a platform solution rather than a point solution for a particular market,” added Rich Rice, senior vice president of business development at ASE.

As reported, fan-out can be sub-divided into two groups—low-density and high-density. And each group has different types of fan-out configurations. For example, eWLB is one type of low-density fan-out package, which is ideal for mobile chips, power management ICs and RF. It’s not the only solution, however. Many of these chips are housed in other packaging types as well.

Fan-out package-on-package (PoP) is an example of a higher density technology. Apple uses TSMC’s fan-out PoP technology in the latest iPhones. Not all smartphones use fan-out. In fact, the dominate technology is still flip-chip BGA for the apps processor.

Then, there is fan-out system-in-package (SiP). In fan-out SiP, “the driver for that would be miniaturization. You would use it in those cases where the size matters more than the cost,” Hunt said.

Clearly, packaging is going in different directions at once. But that’s a good problem for customers. Sometimes, it’s better to have too many options rather than none at all.

Fan-out roadmap (Source: ASE)

Fake nodes
In a recent article, I addressed an ongoing trend in the IC business: Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers.

At ISS, a panel addressed some of the same issues. One of the first issues the panel addressed is obvious—What are nodes? Today, there are full nodes, but some are pushing quarter and half nodes. Some nodes are more real than others, at least according to one expert. “The panel is going to talk about nodes and something I wrote earlier about the importance that we should not have fake nodes maybe,” said G. Dan Hutcheson, chief executive of VLSI Research, at ISS. “We have fake nodes and we have inter-nodes. It is really complex.”

Fudging the node names is not a new idea. In the 1970s, the industry began to measure nodes by “drawn gate length,” according to Hutcheson. But about that time, some started to use electrical gate length as a measurement, which created some confusion. “We actually had a fake node at that time. It’s what I call a marketing node,” he said.

Over time, the definition of the nodes changed. Then, Moore’s Law became one of the guiding principles. The axiom states that the transistor count doubles on a chip with each process generation. The transistor specs followed the same path.

“Historically, the industry has been following this law, and has named each successive process node approximately 0.7 times smaller than the previous one – a linear scaling that implies a doubling of density,” wrote Mark Bohr, senior fellow and director of process architecture and integration at Intel, in a recent blog. “But recently – perhaps because of the increasing difficulty of further scaling – some companies have abandoned this rule, yet continued to advance node names, even in cases where there was minimal or no density increase. The result is that node names have become a poor indicator of where a process stands on the Moore’s Law curve.”

Intel has proposed a standard metric for the nodes. So far, though, the proposal has followed on deaf ears.

So what is a real node? “Full nodes, at least from an Intel perspective, need to target close to a 2X transistor density improvement compared to the previous node,” Bohr said at the ISS panel. “Full nodes are also where we typically introduce major technology changes, such as high-k/metal-gate and finFETs. Inter-nodes are where you do further optimization on that full node.”

What customers want
Then, the panel dove into what will make future scaling happen. Clearly, the industry is begging for extreme ultraviolet (EUV) lithography at 7nm and/5nm.

Other tools are required as the industry moves towards more complex structures and materials. For example, the industry requires atomic-level processes, such as atomic layer deposition (ALD) and atomic layer etch (ALE).

In logic, for example, the structures are 3D-like in nature. FinFETs are one example. Contact-over-gate is another. At the same time, material systems are becoming more complex and modular in nature. “We see a big change in the way we think about materials,” said Prabu Raja, senior vice president of the Semiconductor Products Group at Applied Materials, at the panel. “You cannot think of it as a unit of materials now. You have to think about materials systems. We see that the number of materials is increasing in the periodic table. We are stacking multiple materials. And now we see variants of materials within each material.”

EUV, atomic-level processes and materials are a given. As before, though, the industry requires new breakthroughs in the backend-of-the-line (BEOL), where the tiny copper wiring schemes are made. The wiring schemes or interconnects are becoming more congested at each node, causing resistance-capacitance (RC) delays.

Interconnect layers in ICs (Source: Lam Research)

Still, foundry customers want the industry to overcome the RC delay issues and scale the interconnects. Today, Intel’s 10nm process has a 36nm metal pitch. The foundries offer processes with slightly larger metal pitches.

One GPU maker wants more. “I really need very dense intensive metal lines,” said John Chen, vice president of technology and foundry management at Nvidia, during the panel. “I need not only new materials, but I need new structures. I need 30nm. 36nm is great. I need even smaller, because I have so much metal interconnect for 5,000 cores. I have such massive parallel processing. When you get into image recognition, you need parallel processing. I need to go in and out of either the cache or to the DRAM. And that takes a lot of interconnect. I need dense interconnect. So I need a smaller pitch and I need new materials.”

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