What’s In The Package?

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it’s also creating its own set of issues around verifying and testing these devices.

This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is something like crossing an SoC with a PCB. But there are a number of new problems that creep into packaging that need to be understood, standardized and eventually automated.

First, there has been so much experimentation with advanced packaging that there is no single best option. There are multi-chip modules, systems-in-package, fan-outs, fan-ins, 2.5D, 3D IC, package-on-package, direct bond, as well as packageless solutions. And there are multiple flavors of each of those, which can vary by what chips and IP are included in the package and which applications they are being targeted for. In addition, there are multiple types of packages themselves, as well as different interconnect materials and bonding/debonding methods, all of which have an impact on thermal and structural stress, quality over time (aka reliability), and degradation due to aging and other factors. So just understanding one type of packaging is no guarantee that another type of package will behave exactly the same way.

Second, EDA tools and flows in this area are incomplete. There are a raft of very capable layout, place-and-route, and simulation tools for everything from chip to package to substrate. There are tools to keep track of different IP (soft and hard) versions and characterizations. But there are so many possibilities when it comes to packaging that it’s hard to choose a starting point. While the individual chips in a package can be designed and debugged using all of the same techniques available for a single 16/14nm ASIC, adding more chips in close proximity can create all sorts of unwanted effects such as noise and heat that are difficult to assess.

Third, this gets even more complicated because the specs for what constitutes a known good die on a board are different than what constitutes a known good die in a package. SoC vendors have been wrestling with this for years, because use cases for a mobile device can vary greatly from one consumer to another. That can limit performance, or worst case it can cause fatal errors. How chips behave under different use cases in packages can vary significantly, and depending upon the type of advanced package, debugging has little or no precedent in this context. This is not the same as putting chips on a PCB, or even the old MCMs. Distances are much shorter, clock frequencies can be higher, and thermal migration can lead to warpage and stresses in places that are not obvious.

Fourth, testing is much more difficult in some packages than others because not all of the leads are exposed. Test methodologies and equipment are evolving with new packaging options, and they include everything from built-in self-test (BiST), which is well understood, to system-level test, which is relatively new. But along with that, statistical analysis will be required for pre- and post-production data to mine data and map issues and trends. This requires a lot more work on the back end of the flow, and a better understanding of how data can impact quality on the front end.

There are plenty of efforts underway to add some structure and predictability into advanced packaging, from fan-outs to MCMs to 2.5D flows. And there are plenty of technical reasons to consider advanced packaging, including better performance, lower power and flexibility in form factors, time to market and overall cost. That has pushed a number of advanced packaging approaches into the mainstream for server and networking chips, various memories, and even smart phones and graphics cards.

But none of this is as simple as stringing IP blocks or chips together based upon what’s available at any point. Making sure everything works together properly remains a challenge, particularly when different vendors provide various chips within a package. And while work is underway on a number of fronts to simplify this process by narrowing down the number of options, there is still much work to be done.