How 5G Is Influencing Silicon Design

By Synopsys - 21 Dec, 2020 - Comments: 0

5G is introducing a wide array of challenges in next-generation SoCs that go well beyond high bandwidth wireless. These include increasing system bandwidth, lowering SoC latency, and reducing power significantly for the connected internet of things. Using trusted standards-based IP and proven processing and analog IP at the most aggressive process technology nodes is needed to bring 5G to marke... » read more

Week In Review: Design, Low Power

By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

IP Safe Enough To Use In Cars

By Ed Sperling - 07 Dec, 2020 - Comments: 0

IP that is used for functional safety needs to respond to events that can happen, whether those are planned or random. Jody Defazio, vice president of IP quality and functional safety at Synopsys, talks with Semiconductor Engineering about ASIL compliance, what the different levels mean, and the impact of using chips developed at the most advanced process nodes in automotive applications. » read more

Change Management With Impact Analysis During Safety-Critical IP And SoC Development

By Synopsys - 07 Dec, 2020 - Comments: 0

Standards like ISO 26262 provide guidance to mitigate safety risks by defining safety analyses requirements and processes. The standard describes Change Management as a way to analyze and control changes in safety-related work products, items, and elements throughout the safety lifecycle. Impact analysis, a part of the Change Management process, is a systematic approach for evaluating changes t... » read more

Designs Beyond The Reticle Limit

By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

The Benefits Of Using Embedded Sensing Fabrics In AI Devices

By Moortec - 11 Nov, 2020 - Comments: 0

AI chips, regardless of the application, are not regular ASICs and tend to be very large, this essentially means that AI chips are reaching the reticle limits in-terms of their size. They are also usually dominated by an array of regular structures and this helps to mitigate yield issues by building in tolerance to defect density due to the sheer number of processor blocks. The reason behind... » read more

Week In Review: Design, Low Power

By Jesse Allen - 16 Oct, 2020 - Comments: 0

Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

EDA, IP Show Surprising Strength

By Ed Sperling - 06 Oct, 2020 - Comments: 0

EDA and IP revenue surged 12.6% in Q2 to $2.78 billion, up from $2.47 billion in the same period in 2019, according to a just-released report. That growth occurred in all regions, as well. What's surprising about the report is just how strong sales were in the midst of the COVID-19 pandemic. "Revenue was up strongly from Q1, and there was enormous growth," said Wally Rhines, executive spo... » read more

112G SerDes Reliability

By Ed Sperling - 05 Oct, 2020 - Comments: 0

Priyank Shukla, product marketing manager at Synopsys, digs into 112Gbps SerDes, why it’s important to examine the performance of these devices in the context of a system, what is acceptable channel loss, and how density can affect performance, power and noise. » read more

Deals That Change The Chip Industry

By Ed Sperling - 28 Sep, 2020 - Comments: 0

Nvidia's pending $40 billion acquisition of Arm is expected to have a big impact on the chip world, but it will take years before the effects of this deal are fully understood. More such deals are expected over the next couple of years due to several factors — there is a fresh supply of startups with innovative technology, interest rates are low, and market caps and stock prices of buyers ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: IP

How 5G Is Influencing Silicon Design

Week In Review: Design, Low Power

IP Safe Enough To Use In Cars

Change Management With Impact Analysis During Safety-Critical IP And SoC Development

Designs Beyond The Reticle Limit

The Benefits Of Using Embedded Sensing Fabrics In AI Devices

Week In Review: Design, Low Power

EDA, IP Show Surprising Strength

112G SerDes Reliability

Deals That Change The Chip Industry