tag: IP

Power Management And Integration Of IPs In SoCs: Part 1
By Progyna Khondkar - 09 Apr, 2020 - Comments: 0

IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

A New Era In Flexible, Affordable Design
By Phil Burr - 09 Apr, 2020 - Comments: 0

Socionext has always prided itself on flexibility. The company was formed in 2015 as part of the merger of the LSI businesses of Fujitsu and Panasonic. So not only did the company successfully merge engineering teams, it’s grown and expanded its offerings of advanced systems-on-chips (SoCs) over the years. As such, Socionext’s philosophy is rooted in doing more than just listening carefu... » read more

Tracking Automotive’s Rapidly Shifting Ecosystem
By Ann Mutschler - 02 Apr, 2020 - Comments: 0

The automotive ecosystem is becoming much harder to navigate as automakers, Tier 1s and IP vendors redefine their relationships based upon shifting value caused by an rapidly expanding amount of increasingly interdependent and complex electronic content. Predictions of massive change started almost a decade ago with a number of pilot programs around autonomous vehicles. But those shifts real... » read more

More Multiply-Accumulate Operations Everywhere
By Ed Sperling - 02 Apr, 2020 - Comments: 1

Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

Medical, Industrial & Aerospace IC Design Changes
By Ann Mutschler - 30 Mar, 2020 - Comments: 0

Medical, industrial and aerospace chips are becoming much more complex as more intelligence is added into these devices, forcing design teams to begin leveraging tools and methodologies that typically have been used only at the leading-edge nodes for commercial applications. But as with automotive, the needs of these systems are changing quickly. In addition to strict quality, safety and sec... » read more

Why It’s So Hard To Create New Processors
By Brian Bailey - 26 Mar, 2020 - Comments: 1

The introduction, and initial success, of the RISC-V processor ISA has reignited interest in the design of custom processors, but the industry is now grappling with how to verify them. The expertise and tools that were once in the market have been consolidated into the hands of the few companies that have been shipping processor chips or IP cores over the past 20 years. Verification of a pro... » read more

Do You Trust Your IP Supplier?
By Brian Bailey - 26 Mar, 2020 - Comments: 0

How much do you trust your IP supplier, regardless of whether IP was developed in-house or by a third-party provider? And what implications does it have a system integrator? These are important questions that many companies are beginning to ask. Today, there are few methods, other than documentation, that provide the necessary information. The software industry may be ahead of the hardware i... » read more

Designing Resilient Electronics
By Ann Mutschler - 18 Mar, 2020 - Comments: 0

Electronic systems in automobiles, airplanes and other industrial applications are becoming increasingly sophisticated and complex, required to perform an expanding list of functions while also becoming smaller and lighter. As a result, pressure is growing to design extremely high-performance chips with lower energy consumption and less sensitivity to harsh environmental conditions. If this ... » read more

Timing Closure At 7/5nm
By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Die-to-Die Connectivity With High-Speed SerDes PHY IP
By Manuel Mota - 12 Mar, 2020 - Comments: 0

Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

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