Making Sure RISC-V Designs Work As Expected


The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

Using Automotive IP For Easier Integration Of Safety Into SoCs


By Shivakumar Chonnad and Vladimir Litovtchenko Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of S... » read more

Can You Afford To Waste Time On Your Next Design Project?


Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and ... » read more

Security Risks In The Supply Chain


Semiconductor Engineering sat down to discuss security in the supply chain with Warren Savage, research scientist in the Applied Research Laboratory for Intelligence and Security at the University of Maryland; Neeraj Paliwal, vice president and general manager of Rambus Security; Luis Ancajas, marketing director for IoT security software solutions at Micron; Doug Suerich, product evangelist at ... » read more

EDA, IP Growth Surge


EDA and IP grew 8.9% in Q3 of 2019, according to a just-released report, indicating continued confidence in semiconductor growth. Total revenue was up 8.9% globally compared with the same period in 2018, but that number is deceptively low. Revenue in China, for example, increased 5.7% compared to the same quarter in 2018, despite trade restrictions on sales of any IP developed in the United ... » read more

Crossed Wires On Domains


Clock, power and reset domains can form a tangled web if systems are not architected correctly. Wires that cross these domains often require special treatment and additional analysis. They are all evolving independently, meaning that designers must keep up with the latest methodology guidelines and tool capabilities to ensure problems do not remain hidden until they get exposed in silicon. C... » read more

A Promising Future For Interconnect IP


Complexity of SoC designs continues to increase primarily due to increased demand for functionality and performance in all electronic devices. Studies that Semico Research has conducted on the SoC design landscape shows the number of discrete SIP blocks has continued to rise in response to increased market requirements from new applications and richer feature sets. Table 1: Comparison of 1st... » read more

A New Dawn For IP


The IP industry is changing again. The concept started as build once, use everywhere, but today it is more like architect once, customize everywhere. Few designs can afford sub-optimal IP for their application. The need for customized IP is driven by both leading-edge designs and the trailing markets, although for different reasons. While this customization is causing IP companies to transfo... » read more

Challenges In IP Reuse


Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

Finding Hardware Trojans


John Hallman, product manager for trust and security at OneSpin Technologies, looks at how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised. » read more

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