tag: IP

Portable Stimulus Status Report
By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 24 Aug, 2017 - Comments: 0

Aart de Geus, chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], sat down with Semiconductor Engineering to discuss machine learning and big data, the race toward autonomous vehicles, systems vs. chips, software vs. hardware, and the future of EDA. What follows are excerpts of that conversation. SE: The whole tech world is buzzing over data and how it gets used in areas such as... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

IP Biz Changes As Markets Fragment
By Ed Sperling - 22 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"]' S... » read more

IP Challenges Ahead
By Brian Bailey - 10 Aug, 2017 - Comments: 0

The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

System Performance Analysis At ARM
By Arm - 09 Aug, 2017 - Comments: 0

Performance analysis is a vital task in modern SoC design. An under-designed SoC may run too slowly to keep up with the demands of the system. An over- designed SoC will consume too much power and require more expensive IP blocks. At ARM we want to help our partners build SoCs that deliver the best performance within their power and area budgets. The simple truth is that this is more difficu... » read more

Packaging Enters New Phase
By Ed Sperling - 07 Aug, 2017 - Comments: 0

The race is on to make advanced packaging less expensive than shrinking everything down onto the same die—much less expensive, in fact. Following several years of speculation and rather shaky market predictions at the beginning of this decade, packaging houses and foundries spent the last four years proving that packaging really does provide a viable alternative to shrinking die in terms o... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

How To Close Timing With An eFPGA Hosted In An SoC
By Volkan Oktem - 03 Aug, 2017 - Comments: 0

eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more

Hybrid Emulation
By Brian Bailey - 19 Jul, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

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