IP Biz Changes As Markets Fragment

Experts at the Table, part 2: Tracking IP and potential issues; dealing with multiple versions of the same IP; the impact of advanced packaging; will there be more IP startups?

popularity

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of ClioSoft; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for Cadence‘s IP Group; and John Koeter, vice president of marketing for Synopsys‘ Soutions Group. What follows are excerpts of that conversation. To view part one, click here.

SE: If you have an SoC being manufactured at an advanced node for one foundry, and then that chip moves to another foundry, what happens to the IP?

Anantharaman: It can be challenging to track that IP, especially cloned relationships. For one process node you’ve created an IP, and then three times maybe you’ve done something else. So that’s really a different IP. But you still need to track the relationship that ‘this IP’ was cloned from ‘this one.’ That becomes important for a different reason, too. If you find an issue in the original IP, it probably relates to all the clones of that IP.

Galloway: IP vendors have developed design flows that are different from what an IDM would have. An IDM would sit in the process, maybe develop their own internal flows and processes for IP. As an IP vendor, we have customers that are at 7nm and customers that are at 180nm, and we have customers at many different foundries. We have to develop flows to mitigate that.

Koeter: We have a golden architecture and a golden CAD flow, and then we have low-cost portings all over the world. We take those and crank them through low-cost portings so we can take advantage of many different processes at a reasonable cost point.

Greenberg: The customers are going to change foundries and we have to be ready for that.

Galloway: Yes, and some of it is driven by the IP vendor. But much of it is driven by the customers. Customers are driving the foundries, and IP vendors are following the customers.

SE: So how can IP vendors deal with this without creating new IP every time?

Koeter: You have to be very efficient with multi-site development. To a certain extent you have to have a factory productivity model.

Galloway: Beyond the golden architecture, the IP has to be robust and architected in a way so that it can be targeted across multiple nodes and foundries without re-architecture. We’re spending a lot more time on the architecture so duplication can be done efficiently.

Greenberg: The customers have the same issues as we do. They may delay their foundry decisions until the last minute for all kinds of reasons, and then they need to get the chip done in a very short time scale. So the IP vendor needs to be there and ready for them.

Koeter: You have to be there and ready to react. And the more you can anticipate the foundry variations, the more you can have one architecture. There’s no reason why you can’t design one GDS II implementation that covers multiple 16nm processes, and have one master design where you take a superset approach.

SE: What happens when we move into advanced packaging? How does that change the dynamics here? Do you now have to go back and re-characterize everything?

Koeter: One of the things we’ve been worried about for a long time is whether that will change the fundamental partitions that people have been doing for a long time. The answer appears to be no.

Greenberg: There is some hypothetical panacea—and we’re not there yet—where you may have a 2.5D chip and you do all of your logic in the very best logic process, a memory done in the very best memory process, and you put down a SerDes done in the very best SerDes process, and then you connect them all together with an interposer. That’s great if the interposer comes at a reasonable price, but that hasn’t happened yet.

Koeter: 2.5D has enormous potential, but it’s still too expensive.

Greenberg: When people go there it’s because of bandwidth, either chip-to-chip or chiplet-to-chiplet. The classic example now is an HBM2 memory. You do that with 2.5D integration because you can put down a massive number of microbumps on one chip and a massive number on another, and then you get a very wide parallel interface between the two. In the case of HBM2 you get 2 terabits per second of memory bandwidth between the SoC and the HBM2. If you need that much bandwidth, that is the cheapest option, particularly in comparison to massive amounts of DDR4. The HBM2 will give you much more bandwidth, and if your metric is dollars per gigabits per second if that’s the best option. But not everyone needs that metric. Sometimes you just need dollars per chip.

SE: What does that do to IP reuse? Not everything is the latest version, right?

Anantharaman: Correct, and that creates a challenge of being able to track it.

Greenberg: And now you have multiple chips together on a 2.5D interposer. That’s something you need to manage.

Anantharaman: Yes, and you need a consistent way of doing that. So you may have standard IP on each chip, and while you’re developing you may want to go from one rev to another. That all needs to be tracked. There are so many variants, and you need a way to do that efficiently.

Galloway: With system-in-package, a lot of wireless devices are going on one chip, high-end processing on a more advanced chip, and we need SerDes to connect these two. That’s a lot different than using an interposer. There are multiple types of advanced packages for a lot of different applications.

SE: But in general, there seem to be two trends for advanced chips. One is put everything onto one chip at the most advanced nodes. The second is to break these apart into multiple pieces with accelerators and different kinds of memory to improve performance.

Koeter: Somewhere between 80% to 90% of our customers will add their own custom instructions to accelerate certain functionality. Security is one. Safety features are another.

SE: But are the configurations changing? Are people combining these in different ways than in the past?

Greenberg: We’re seeing people sprinkling processors around the chip more often. In the past, you had one CPU on your die. Now you may have hundreds, each one doing a specialized function and doing it very well, but sprinkled throughout the SoC.

Galloway: There are processors are doing many different things. In the past, they were doing things that were very simple. They’re getting more complicated. Now you have programmable control for the calibration. Now there are microprocessors for SerDes. A small microprocessor is addressing a function that 20 years ago wasn’t needed.

Greenberg: Now you can update the firmware for some of these processors, too, which you couldn’t do in the past.

Koeter: We’re seeing more specialization in standard processor families with DSPs, safety islands, security, high-speed versions, closely couple cache, MMU options. There are specialized vision processors. So there is a proliferation of processors even within one processor family because of that specialization.

SE: This isn’t just happening in processors. It’s happening in memory and I/O, as well. So now we’ve got so many different options that it’s getting harder to make choices. What’s the impact of that?

Anantharaman: There are so many IPs that it becomes more difficult to make comparisons. What is similar? What is different? What are the different parameters? Even in the same chip you may have different configurations of the same IP. So maybe you have a dual-core version of a processor here and a quad-core version somewhere else. And for licensing purposes, you have to know all of that.

Galloway: A lot of the product proliferation is customer-driven. An IP vendor wouldn’t choose to make 17 versions of IP if there were already 16 versions available.

Greenberg: But you can model how you want to assemble this system, from early architectural models, where you can swap things in and out. And you take those models through prototyping solutions and through emulation systems and simulation and get this continuum of the verification, emulation and prototyping environment.

SE: Can you also look at this by foundry process and packaging technology?

Greenberg: The packaging technology will definitely make a difference. The foundry may make some difference, and you need to account for that. And the process node will make a difference, too. So you may need to account in that model for a different frequency at a different geometry. That all comes into the model. And then you need to estimate the cost of all of this. You may shoot for the very best target on everything, but you might not be able to afford that. So then, what is the most cost-efficient process and the most cost-efficient way to get the chip done? As an SoC vendor, you’re looking to assemble these into something bigger, so you need to take it up a level of abstraction.

SE: Has the selling process changed?

Koeter: Four years ago we thought the answer was pre-cut, pre-verified subsystems. We still do some of that for specific applications, like embedded vision applications and sensor hubs. But more and more, companies are looking for services around the SoC to customize and harden them and do power integrity analysis.

Anantharaman: Going back 15 years ago, version control was a new thing for the analog folks. It was a missionary sale. Now you go in and they want all these different variants and branches. They’re using issue-tracking systems, so that if there is an issue ‘here’ it is tracked all the way through and you know what the relationships are. You no longer have to pitch to them why you need to track your IP. It’s now part of the methodology.

SE: So what will this industry look like in a few years? Will there be fewer IP vendors?

Galloway: There are fewer and fewer every year. When we started 10 years ago, it was a lot easier to get going. Now a lot of the IP development is at 16/10/7nm. To get going at 7nm is a lot more difficult than at 65nm. Over the last 10 years we’ve seen a significant shakeout. Especially at the leading edge, that trend will continue.

Greenberg: The IP at the leading edge are very aggressive about getting into the smaller geometry nodes. It’s very expensive to design there. For new entrants into the IP industry, it will be expensive.

Galloway: One counterbalancing force is that if you wanted to do a 65nm ASIC a decade ago it was quite expensive. If you look at the cost of a 65nm ASIC over time, that has dropped signficantly. If you wanted to outsource an entire 65nm ASIC, that wasn’t possible 10 years ago. It’s still not common, but it is possible now.

Greenberg: That’s because the IP is there and it has been proven in silicon many times. If I’m a new startup trying to do something at 65nm and trying to compete against established IP vendors, which already have silicon-proven IP, that’s difficult. There are drivers out there for that IP. It becomes very easy to use mature IPs than something from a new entrant into the industry.

Galloway: That’s a good point. IP has really enabled cost reduction at the older nodes.

Anantharaman: We believe the complexity will continue to increase. And if you look at startups, we’ve seen a lot of small startups in the IP business. They’re small enough that they don’t show up at shows like DAC, but there are a lot of them.

Koeter: I agree. I don’t see another huge interface IP vendor coming into the market, or another memory vendor. But there absolutely are opportunities for smaller IP vendors to continue entering the market. In vision processing there are a number of IP vendors out there. In neural networking, there are a number of new entrants. It’s the same for security. These are in specific markets. Embedded FPGAs are another category. There will be niches created and eventually there will be consolidation.