Foundry Wars, Take Two

By Ed Sperling - 25 May, 2017 - Comments: 0

Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn't been taken so far is 9nm. It's not that one foundry's 10nm is the same as another's. Each company defines its nodes differently, and these days comparing nodes is almost m... » read more

Emulation Enabling Automotive Designs

By Frank Schirrmeister - 25 May, 2017 - Comments: 0

Last week at CDNLive in Munich, the key topic at hand was automotive. It was pretty much a theme everywhere, and even had its specific personal track. My personal favorites were Davide Santo’s (NXP’s Architect) keynote on autonomous driving—very inspiring—and Robert Bosch’s overview of how they used emulation in a hybrid setup with ARM Fast Models for IP verification for automotive de... » read more

Reworking Established Nodes

By Ed Sperling - 24 May, 2017 - Comments: 2

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Moore’s Law: Toward SW-Defined Hardware

By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

Building One Interface Subsystem For Multiple IoT SoCs

By Ralph Grundler - 11 May, 2017 - Comments: 0

When designing SoCs for Internet of Things (IoT) applications, designers quickly realize that their most efficient use of resources will result in chips that can address multiple end applications. Consumer products require connectivity or edge devices, and networking or enterprise companies are broadening their reach to home networking and cloud services, like remote processing, that complement... » read more

Intel Inside The Package

By Ed Sperling - 08 May, 2017 - Comments: 1

Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

IIoT Grows, But So Do Risks

By Jeff Dorsch - 04 May, 2017 - Comments: 1

By Jeff Dorsch & Ed Sperling After years of fitful progress, [getkc id="78" kc_name="Industrial Internet of Things"] technology is gaining adoption on the factory floor, in the electrical power grid, and other areas that could do with greater amounts of data analysis and insights from a connected ecosystem. AT&T, General Electric, IBM, Verizon Communications, and other large ... » read more

Secret Sauce To Make Design Reuse A Reality

By Ranjit Adhikary - 04 May, 2017 - Comments: 0

In a globally competitive landscape, IP reuse and effective team collaboration play a crucial role in product success. But if one considers the complex dynamics of all the recent advances in technology, the insatiable appetite for consumer electronics coupled with the design cost and time-to-market pressures on designers, one would not be unjustified in assuming that the problem of design reuse... » read more

Verification And The IoT

By Ed Sperling - 04 May, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Performance-IP: Less Memory Latency

By Ed Sperling - 02 May, 2017 - Comments: 0

The combination of more functionality on chips plus more contention for memories is forcing companies to look at different ways to improve performance. Just adding more processing power doesn't guarantee improved performance, and throwing more memory at a problem—either SRAM or multiple levels of cache—is expensive and not always faster. There are too many processors and too many request... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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