tag: IP

The Next Level Of Abstraction For System Design
By Frank Schirrmeister - 24 Sep, 2015 - Comments: 1

Recently there have been a lot of discussions again about the next level of design abstraction for chip design. Are we there yet? Will we ever get there? Is it SystemC? UML/SysML perhaps? I am taking the approach of simply claiming victory: Over the last 20 years we have moved up beyond RTL in various areas—just in a fragmented way. However, the human limitations on our capacity for processin... » read more

The Price Of Consolidation
By Ed Sperling - 24 Sep, 2015 - Comments: 0

Consolidation is causing far-reaching changes across the global semiconductor ecosystem due to the size of companies being bought and the dearth of startups to replenish those being acquired. Coupled with the rising cost and difficulty of shrinking features down to advanced process nodes—many argue that is the largest driver of consolidation—the market dynamics for who's buying IP, EDA t... » read more

FinFET Technology
By Synopsys - 23 Sep, 2015 - Comments: 0

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to... » read more

ESL: 20 Years Old, 10 To Go
By Brian Bailey - 23 Sep, 2015 - Comments: 2

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Appetite For Services Grows
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

Tech Talk: Power Emulation
By Ed Sperling - 10 Sep, 2015 - Comments: 0

Jean-Marie Brunet, marketing director for Mentor Graphics' Emulation Division, talks about why hardware-assisted verification is now required for power and where it works best. [youtube vid=Mb63cbjbZ_I] » read more

Shift In Focus For Low Power Design
By Alan Gibbons - 10 Sep, 2015 - Comments: 0

The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high... » read more

Anatomy Of The HDMI IP Certification Flow
By Synopsys - 09 Sep, 2015 - Comments: 0

HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow f... » read more

Blog Review: Sept. 9
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

The Week In Review: Design/IoT
By Ed Sperling - 04 Sep, 2015 - Comments: 0

IP Synopsys rolled out logic library and embedded memory IP for the Mie Fujitsu 40nm low-power process. The process has 50% lower power consumption compared with previous process technologies. Deals Rambus' Cryptography Research Division won a deal to run the Secure Content Storage Association's cryptographic key management center. The keys are used in SCSA-enabled devices for securing vid... » read more

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