Week 47: The Yin And Yang of DAC

By Anne Cirkel - 01 May, 2015 - Comments: 0

In one of my early blog posts I explained that DAC is owned by three non-profit societies: ACM, IEEE/CEDA and EDAC. While the executive committee right now is working on a successful 52nd DAC, planning for future events has already started. Future locations are usually booked years in advance as most of convention center and hotel contracts are signed at least 18 months out. The financial liabi... » read more

Problems Ahead For EDA

By Brian Bailey - 27 Apr, 2015 - Comments: 0

You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

What Not To Verify

By Ann Mutschler - 23 Apr, 2015 - Comments: 0

It is well understood that [getkc id="10" kc_name="verification"] is all about mitigating and managing risk, and success here begins with a good verification planning process. During the planning process, the project team creates a list of specific design functions and use cases that must be verified—and they identify the technique used to verify each specific item on the list. That list c... » read more

What EDA’s Big 3 Think Now

By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Is Art Acceptable In Verification?

By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow

By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Tech Talk: Virtual Prototyping

By Brian Bailey - 22 Apr, 2015 - Comments: 0

Bill Neifert, CTO of Carbon Design Systems, talks with about the intersection of IP and EDA, driven in particular by ARM's new architecture. [youtube vid=1OopYWmRarE] » read more

EDA Sets New Record

By Ed Sperling - 13 Apr, 2015 - Comments: 0

EDA revenue grew 11.9% in Q4 2014 to $2.1 billion, a new record for the industry, propelled by strong growth in both IP and physical design. On a sequential basis, that represented a 15.1% increase, while on a year-over-year basis it was 11.9%. The four-quarter moving average, which takes into account quarterly aberrations, showed a 7.3% increase. "The semiconductor industry had a strong ... » read more

Ethernet In The Connected World

By Synopsys - 08 Apr, 2015 - Comments: 0

This white paper outlines the latest networking trends across some of the key market sectors including automotive, the connected home and data centers, and explains how Ethernet is relevant to each. It also explains how Synopsys responds to its customers’ needs to develop and offer configurable semiconductor IP that enables system-on-chip (SoC) design teams to quickly and reliably implement E... » read more

Will Wearables Work Well Enough?

By Ed Sperling - 02 Apr, 2015 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler The rollout of the Apple Watch later this month has reset expectations for the wearable electronics market, just as early implementations of the Pebble, Fitbit and Google Glass helped raise awareness about a new level of portability and connectivity. Early projections are for strong sales, which in turn will propel a new level of connectedness for the ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.