tag: Intel

Week In Review: Design, Low Power
By Jesse Allen - 20 Nov, 2020 - Comments: 0

Synopsys acquired Light Tec, a provider of optical scattering measurements and measurement equipment. The company also provides optical engineering consulting services plus training for use of Synopsys' lighting simulation software. "Light Tec's proven optical measurement capabilities provide our customers with robust new tools for high-accuracy optical product simulations and visualizations," ... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 20 Nov, 2020 - Comments: 0

Pervasive computing — Data centers, cloud, 5G, edge In a move to improve data collection for IC manufacturing, PDF Solutions entered a definitive agreement to acquire Cimetrix Incorporated. Cimetrix makes connectivity products for smart manufacturing, which PDF Solutions will use in its Exensio product to facilitate moving IC manufacturing data from the factory floor to cloud-based analytics... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Manufacturing Bits: Nov. 17
By Mark LaPedus - 17 Nov, 2020 - Comments: 0

Intel’s gate-all-around FETs At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors. One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (F... » read more

Disaggregation And Smarter Chips Shift Liability For Security
By Ed Sperling - 17 Nov, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security on chips with Vic Kulkarni, vice president and chief strategist at Ansys; Jason Oberg, CTO and co-founder of Tortuga Logic; Pamela Norton, CEO and founder of Borsetta; Ron Perez, fellow and technical lead for security architecture at Intel; and Tim Whitfield, vice president of strategy at Arm. What follows are excerpts of that conversation,... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 13 Nov, 2020 - Comments: 0

Automotive Cadence achieved ASIL Level B in support of D (ASIL B(D))-compliant certification for its Tensilica ConnX B10 and ConnX B20 DSPs, which are designed for automotive radar, lidar, and vehicle-to-everything (V2X). SGS-TÜV Saar certified that the DSPs have support for random hardware faults and systematic faults. Synopsys is acquiring Moortec, whose process, voltage, and temperature... » read more

Designs Beyond The Reticle Limit
By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

Blog Review: Nov. 11
By Jesse Allen - 11 Nov, 2020 - Comments: 0

Mentor's Chris Spear proposes mixing together the compactness of the field macro style with the preciseness of the do methods when writing a UVM transaction class. Cadence's Paul McLellan looks back at the history of EPROM, some of the difficulty with actually erasing it, and the subsequent development of EEPROM. Synopsys' Tuomo Untinen explains three WPA2 authentication vulnerabilities r... » read more

Blog Review: Nov. 4
By Jesse Allen - 04 Nov, 2020 - Comments: 0

Arm's Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint. Mentor's Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try. ... » read more

Security Tradeoffs In Chips And AI Systems
By Ed Sperling - 03 Nov, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the cost and effectiveness of security in chip architectures and AI systems with with Vic Kulkarni, vice president and chief strategist at Ansys; Jason Oberg, CTO and co-founder of Tortuga Logic; Pamela Norton, CEO and founder of Borsetta; Ron Perez, fellow and technical lead for security architecture at Intel; and Tim Whitfield, vice president of s... » read more

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