tag: lithography

Tech Talk: Double-Triple Patterning
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

The Human Bottleneck
By Ed Sperling - 10 Dec, 2015 - Comments: 0

The history of semiconductor technology can be neatly summed up as a race to eliminate the next bottleneck. This is often done one process node at a time across an increasingly complex ecosystem. And it usually involves a high level of frustration, because the biggest problems stem from areas where engineering teams generally can't do anything about them. Concerns over the years have ranged ... » read more

More Choices, Less Certainty
By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

Resetting Expectations On Multi-Patterning Decomposition And Checking
By David Abercrombie - 22 Oct, 2015 - Comments: 0

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

First Look: 5nm
By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

Mask Supply Chain Preps For 10nm
By Dylan McGrath - 17 Sep, 2015 - Comments: 0

As the semiconductor industry gears up for the 10nm logic node—now likely to begin in the second half of 2017—the photomask supply chain is preparing to grapple with the associated challenges, including dramatic increases in photomask complexity, write times and data volumes. The 10nm node will require more photomasks per mask set, the ability to print smaller and more complex features, ... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Memory Hierarchy Shakeup
By Mark LaPedus - 16 Sep, 2015 - Comments: 0

It’s no secret that today’s memory chips and storage devices are struggling to keep up with the growing demands in data processing. To solve the problem, chipmakers have been working on several next-generation memory types. But most technologies have been delayed or fallen short of their promises. But after numerous delays, a new wave of next-generation, nonvolatile memories are finally ... » read more

How Long Will FinFETs Last?
By Ann Mutschler - 13 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22865" e_name="Samsung"]; and Vic... » read more

Why DSA Is Cost Effective For 7nm And Below
By Yuansheng Ma - 30 Jul, 2015 - Comments: 0

The upcoming 7nm process node presents tough challenges both for printability and cost. At 7nm and below, multi-patterning is required, which makes the manufacturing process more expensive by requiring more masks. To control costs, any alternative technology that provides equivalent yields with fewer patterning steps should be explored. One promising option is to use directed self-assembly (... » read more

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