Where Is Next-Gen Lithography?

Experts at the table, part 2: Issues with current immersion lithography at 7nm and 5nm; EUV vs. DSA and nanoimprint.


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and , chief executive of D2S. What follows are excerpts of that conversation. To view part one, click here.

SE: Technically, 193nm immersion is not a next-generation lithography (NGL) technology, but it is still the workhorse in the fab. What are some of the issues with 193nm immersion and multi-patterning as the industry extends it from 16nm/14nm to 10nm and perhaps beyond?

Levinson: We are all seeing certain issues. A big one is cycle time. If I just add a lot of masking steps, it simply means I now need several more weeks for each cycle of learning. If you need 10 to 20 cycles of learning to get to yield, and you take an extra three or four weeks, you are looking at an extra year in your development cycle to get to where you need for that yield. So, it’s taking longer to get through each cycle of learning. That’s a factor. And that’s a big motivation for using EUV. So you can do all of these multiple patterning steps. It’s just very challenging. You have to put a lot of smart engineers on it. But at some point, you might have to decide life would be easier if you could do it with one exposure with EUV.

SE: So how far can we really extend 193nm immersion and multi-patterning?

Levinson: Certainly, self-aligned quadruple patterning is something we all feel pretty comfortable with. There you are looking at a pitch of 20nm. That’s something we can look at and say: ‘We can do that by tightening up the current processes we are using.’ As an industry, we are pretty good at tightening up processes. So that can go a long way. Then, it comes back to this: ‘I can make those nice lines and spaces very tight. But how many cuts do I need and what are the placements for those. I can make fine pitches. These deposition tools and things like that can get narrow dimensions. But to make contact holes for these dimensions is a lot more challenging.’ So again, that’s where the stress is going to be if we want to do it optically.

Mitra: You can also look at the memory industry. They have gone through some of the pain. It’s a little easier now. In terms of planar NAND, for example, suppliers went to 15nm and 16nm with multi-patterning. In that case, line/space can be done with multi-patterning. Now, of course, NAND suppliers are going to 3D NAND or V-NAND. DRAM, on the other hand, is on the cusp of several challenges as they extend planar DRAM to 20nm and beyond. Overlay and edge placement are factors. It impacts yield and scaling. Patterning is becoming a huge problem there, especially affordable patterning. In logic, meanwhile, you can do multi-patterning, especially for line/space. But when you do the cuts, it becomes tricky.

Levinson: Certainly, there will continue to be demand for semiconductor devices for a long time. There is demand for devices with increasing functionality. You can use optical for a while longer without EUV. But there are major advantages with EUV. It’s something we can use.

SE: Some say if EUV misses the window at 5nm or so, the industry may need to resort to 193nm immersion with self-aligned octuple patterning (SAOP). Is SAOP even possible?

McIntyre: I don’t think anybody would say we can’t. I’m sure a couple of years ago people thought we would never get to SAQP. So SAOP is potentially feasible to get the lines. If you are doing SAOP, you are looking at sub-20nm pitch type values. To do vias, cuts and blocks, you’re looking at seven, eight, nine or who knows how many exposures in a 193nm world. Economically, it’s hard to imagine that this would be feasible without EUV. So, SAOP might work. It might be that or EUV and SADP. But in order to do the cuts, blocks and vias, EUV will be essential.

Mitra: There are some economic issues with that. There is also overlay. Let’s say you have five exposures. You have to align one to the other. It’s a nightmare.

McIntyre: There have been a lot of innovations in the way we do the patterning integration process. For example, instead of just doing litho-etch and then another litho-etch, you can do something like add a spacer around it to help self-align one process to another. There is an array of these kinds of tricks you can play to do self-alignment.

Mitra: You hear about technologies like spacer-over-spacer. So, there are also a lot of new materials and films involved. With this, you will require highly selective removal techniques with precise control.

SE: As the industry continues to extend optical, what does that mean for the photomask side of the equation?

Hayashi: The extension of 193i will increase the mask numbers per layer. That’s a challenge for us in terms of delivery times. Also, they require a very tight overlay accuracy control. Meanwhile, the layouts are moving towards 1D. So, the OPC features are a little relaxed on each layer. But as I said, the number of layers is increasing. So the total write times and inspection times for one layer are quite long. But the customer expects a similar cost for one layer. So that’s a challenge for us.

Fujimura: The challenge is more on the contact layers. Until EUV comes along, or some other alternative, it will be challenging to make holes or the cuts. So, you may need very, very complex OPC. That may require having more complex shapes on the mask. In turn, what that is going to require is simulation-based processing. This is how we see it playing out until EUV is there.

Hayashi: There are other issues. For example, it’s not easy to continue with such kinds of capital spending investments, especially for merchant mask shops. It’s quite difficult to make these huge capital investments by ourselves. Maybe the solution is to work jointly with others.

SE: Let’s switch to one NGL technology called directed self-assembly (DSA). What’s going on with DSA?

McIntyre: There has been a flurry of DSA activity over the last few years. The barrier of entry to do research for DSA is different. You don’t need new tools. You can do this with the infrastructure we have in place. So it’s allowed people to explore this space and come up with new ways of using DSA. DSA has matured to a point that we at least understand more of what the potential capabilities can be. It still has some significant challenges we need to address. Defectivity is the primary one. We also need to figure out a way to integrate DSA into the design world. It’s the same world that was created around 193nm lithography. That said, there are still a few potential applications for it. The most likely initial one could be in the memory sector with what Imec calls the ‘Chips Flow’ process. It’s basically creating hexagonal arrays of holes. You can do that with a fairly simple DSA process, instead of using multiple-crossed lithography like SADP or SAQP. This could give you a potential cost saving for the memory industry. In addition, this could perhaps withstand the defect levels that DSA has now. Beyond that, there are logic applications. It could be vias. We‘ve talked a lot about the need to create small holes. DSA is very good at making small holes. The challenge is to make them in particular arrangements. This isn’t easy. And line/space patterns can be created with DSA. Again, defectivity is the biggest challenge from a logic perspective. But if we can get past that, it could be a cost-effective alternative to something like SADP.

Levinson: There are particular challenges for logic. To get the types of shrinks we need, we find that we need to have more than a single pitch. Getting that for line/space patterns with DSA is problematic today. Again, when you try to use it for contact and via layers, it’s getting the non-periodic structures that you get in random logic. There also has to be a lot more work done on the lithography design co-optimization side to make this work. There needs to be more work that takes place in terms of creating a low defect process on the wafer. There are still a lot of substantial issues here.

SE: When will DSA happen and what are the initial apps?

Fujimura: In our recent eBeam Initiative survey, we asked the respondents which technology they are the most confident in. Respondents had the most confidence in EUV. Nanoimprint was second. DSA is after that.

McIntyre: We hosted the first DSA symposium this past year. In a survey that came out of this event, there seems to be a pretty good indication that people thought DSA could see its first use in the next two to five years. I interpret that to probably mean in the memory sector. DSA could be used to create hexagonal array capacitor-type patterns. It could happen in two years to replace SADP crossed technology. Or in four or five years, it could replace SAQP, which could become very expensive.

Mitra: Memory is probably going to be the first insertion point, because of the redundancy in these devices. This could be DRAMs or even some of the newer memories.

McIntyre: If DSA happens, you’ll see a mix of both chemo and graphoepitaxy process flows. To make holes, you can do it using a chemo-epitaxial pillar formation type of process. Or you can do it with confining templates in a graphoepitaxial approach. They have different applications and there are pros and cons. But they are both very much on the table today.

SE: What about next-generation DSA materials, sometimes known as high chi?

McIntyre: There is good progress in high chi. For example, we had a recent paper with the University of Chicago and TOK. We added an ionic liquid to PSMMA materials. Basically, they create a stronger entity that turns into a high chi. So, you can do sub-10nm half-pitch imaging with the added benefit of having the same materials that we usually work with. It’s still very much in the research phase and feasibility study stage. The truth is we don’t need those dimensions at this point quite yet. That’s still a couple of years away.

SE: Any other issues?

McIntyre: DSA sometimes has the problem that it can make stuff too small. The typical dimensions that we will work in are 28nm pitch with standard PS-PMMA type of materials. But you can go well below 10nm half-pitch. People have demonstrated DSA down to 4nm or 5nm. It’s all a matter of if you can confine it well enough. It’s also a matter of if you can get hole formation in a nice manner. If you can’t confine it tight enough, then your holes start to move around.

Fujimura: Therefore, placement accuracy would then become an issue.

Hayashi: But even then, we need a cut process.

McIntyre: DSA makes holes. For cuts, you need little slits. So, it’s useful to have elongated holes. DSA makes perfectly circular holes. For some applications, it’s nice. For others applications, it’s challenging. Then, you must think about designing around DSA. You must start from the ground up and design in a DSA world. Is the industry going to do that? It’s hard to say.

Related Stories
Where Is Next-Gen Lithography?
7nm Lithography Choices
Getting Over Overlay
Survey: Mask Complexity To Increase
DSA Defects Continue Downward Trend


Ken Rygler says:

I saw nanoimprint in the subtitle, and no where else.

Mark LaPedus says:

Hi Ken, Stay tuned. It’s a 3 part series.

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