Comparing New Memory Types


After decades of research and development, three new types of memory—magnetic RAM (MRAM), phase change memory (PCRAM) and resistive RAM (ReRAM)—are moving toward commercial adoption, making this an exciting time for the semiconductor and computing industries. All three of these emerging memories are enabled by new materials and will require breakthroughs in process technology and manufactur... » read more

Finding The Bottom Of The Memory Trough


In announcing its Q2 fiscal 2019 results, Micron Technology, Inc. provided lower-than-expected revenue guidance of between $46 billion and $50 billion for the current quarter. However, what was particularly noteworthy was the company’s announcement to cut output by 5 percent due to weaker-than-expected market demand and its prediction that its customers’ inventory correction will last until... » read more

More Memory And Processor Tradeoffs


Creating a new chip architecture is becoming an increasingly complex series of tradeoffs about memories and processing elements, but the benefits are not always obvious when those tradeoffs are being made. This used to be a fairly straightforward exercise when there was one processor, on-chip SRAM and off-chip DRAM. Fast forward to 7/5nm, where chips are being developed for AI, mobile ph... » read more

GDDR6 And HBM2: Signal Integrity Challenges For AI


In a nutshell, Artificial Intelligence (AI) and its growing list of applications demand a considerably large amount of bandwidth to push bits in and out of memory at the highest speeds possible. AI has been getting a lot of industry attention, and certainly it’s not a new phenomenon because it’s been gaining even greater traction in the last year or two. This is especially true since a n... » read more

Target: 50% Reduction In Memory Power


Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Optimization Challenges For Safety And Security


Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together. Design teams are now dealing with the impl... » read more

Blog Review: April 10


Arm's Paul Whatmough discusses the growing use of real-time computer vision on mobile devices and proposes transfer learning as a way to enable neural network workloads on resource-constrained hardware. Cadence's Anton Klotz highlights a collaboration with Imec and TU Eindhoven on cell-aware test that reduces defect simulation time by filtering out defects with equivalent fault effects. M... » read more

GDDR6 – HBM2 Tradeoffs


Steven Woo, Rambus fellow and distinguished inventor, talks about why designers choose one memory type over another. Applications for each were clearly delineated in the past, but the lines are starting to blur. Nevertheless, tradeoffs remain around complexity, cost, performance, and power efficiency.   Related Video Latency Under Load: HBM2 vs. GDDR6 Why data traffic and bandw... » read more

3D NAND Metrology Challenges Growing


3D NAND vendors face several challenges to scale their devices to the next level, but one manufacturing technology stands out as much more difficult at each turn—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems and ensure yields for all chip types. In the case of 3D NAND, the metrology tools are becoming more expensive at each iteration... » read more

Memory Architectures In AI: One Size Doesn’t Fit All


In the world of regular computing, we are used to certain ways of architecting for memory access to meet latency, bandwidth and power goals. These have evolved over many years to give us the multiple layers of caching and hardware cache-coherency management schemes which are now so familiar. Machine learning (ML) has introduced new complications in this area for multiple reasons. AI/ML chips ca... » read more

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