System-Level Verification Tackles New Role


Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

Deep Space Design Considerations


The linchpin technology in a deep space telescope is the ability to efficiently convert analog image sensor data into digital data in order to beam home high-resolution images of astronomical objects. The analog-to-digital converters (ADC) must perform flawlessly once deployed, because it is not feasible to drive out 1 million miles into space to fix any problems. The next-generation success... » read more

Analog-To-Digital Conversion Is Key For Deep Space Exploration With The James Webb Space Telescope


Reflect back to your last design project. Did it have leading-edge requirements that seemed impossible at the time to fulfill? Now think about a design that needs to live in the harsh environment of space. A device that has to sip power and function flawlessly for over a decade because there is no opportunity to service it if anything goes wrong. That is the set of requirements that faced Dr. L... » read more

Blog Review: April 27


In a video, Cadence's Chris Rowan looks at the future of neural networks, particularly the shift from cloud-based to embedded devices and what we can increasingly expect from them. Waiting for RTL? Mentor's Rich Edelman suggests a way to get tests that are missing some simple RTL running with a bit of SystemVerilog. Synopsys' Richard Solomon provides a primer on calculating the bandwidth ... » read more

10nm Versus 7nm


The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm. But the landscape is complicated, with each vendor taking a different strategy. [getentity id="22865" e_name="Samsung"], for one, plans to ship its 10nm [getkc id="185" kc_name="fi... » read more

7nm Fab Challenges


Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

ECOs and Multi-Patterning: It Can Be Done


By David Abercrombie and Alex Pearson A lot has been written and discussed about how to decompose (color) layouts for advanced process nodes that require multi­patterning (MP). However, one topic that has been sorely ignored is how to efficiently make changes to designs that are already colored, or even taped out and processed. We tend to act like all designs work out the first time through... » read more

Calibre xACT Parasitic Extraction Supports Signal Integrity At Advanced Nodes


At advanced nodes, signal integrity analysis requires precise characterization, which in turn requires an accurate extracted netlist. Models that handle new impacts on parasitic extraction at advanced nodes, including multi-patterning, finFETs, and resistance and capacitance effects, must be used. Learn how the Calibre xACT extraction tool supports these advanced foundry device models and leadi... » read more

Blog Review: April 20


Synopsys' Michael Posner digs into the relationships between USB Type-C, USB 3.1, Power Delivery and DisplayPort specifications. Cadence's Paul McLellan listens in on a discussion of the memory market's growth in China, and what's on the horizon. Mentor's Andy Macleod looks at the challenges that come with the increased car customization consumers are demanding. An energy-harvesting, t... » read more

Rightsizing Challenges Grow


Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

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