The New Face Of Formal

By Brian Bailey - 29 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

3D Thermal Simulation Of Resistive Heating

By Robin Bornoff - 29 Oct, 2015 - Comments: 0

Joule heating, also known as resistive or Ohmic heating, is the power lost to heat as electrical current flows down a conductor. We were introduced to Joule’s first law (Power dissipation = I²R, VI, V²/R) way back in high school. From an electronics thermal simulation perspective it requires a full 3D electrical flow simulation to be conducted, and from that the Joule heating power dissipat... » read more

10 Common Device Noise Analysis Mistakes

By Mentor, a Siemens Business - 28 Oct, 2015 - Comments: 0

Device noise is critical in nanometer-scale CMOS processes, and it fundamentally limits the performance of many circuits at 45 nm and below. Given the right tools, device noise analysis (DNA) is a fairly straightforward process that should produce results that are within 1 dB to 2 dB of silicon measurements. However, there are a number of common mistakes that can lead to grossly overestimating ... » read more

Blog Review: Oct. 28

By Jesse Allen - 28 Oct, 2015 - Comments: 0

Get up to date on the latest USB 3.1 happenings with Synopsys' Eric Huang, including the first laptops shipping with the Type C connector, the importance of USB safety, and price cuts on chips from Intel and ASMedia. The connected car is ready to hit the mass market, according to automakers, but customer adoption has been slow. Mentor's John Day takes a look at a report from the TU-Detroit c... » read more

Will The Chip Work?

By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

The Week In Review: Design/IoT

By Jesse Allen - 23 Oct, 2015 - Comments: 0

M&A ARM acquired Carbon Design Systems and its staff for an undisclosed sum, adding virtual prototyping capabilities for ARM cores. In 2008, ARM sold Carbon the tools it acquired in the 2004 purchase of virtual prototype development company AXYS Design Automation. Tools Mentor Graphics updated its PADS software, adding 3D tool capabilities to provide visualization, placement, and d... » read more

Resetting Expectations On Multi-Patterning Decomposition And Checking

By David Abercrombie - 22 Oct, 2015 - Comments: 0

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

Double Patterning Custom Design And Debug

By Mentor, a Siemens Business - 22 Oct, 2015 - Comments: 0

Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Taming Mask Metrology

By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Blog Review: Oct. 21

By Jesse Allen - 21 Oct, 2015 - Comments: 0

Ansys' Bill Vandermark goes back to the future in this week's top five picks. Plus, the star of the world's longest hoverboard flight gets an upgrade. Perhaps the person riding it will be wearing an ocean-cleaning bikini. Straight from MemCon 2015, Rambus' Aharon Etengoff brings us a keynote exploring the increasingly blurred lines between memory and storage, and how an alternative paradigm ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?