Week 40: Look Who’s Talking


I have to admit I feel like a child bursting with excitement to announce our designer keynote for Monday’s opening session at DAC. Brian Otis from Google will give a talk entitled, “Google Smart Lens: IC Design and Beyond.” The project made news last summer with the announcement of a licensing deal between Google and Novartis to develop technology to help manage diabetes. It will be great... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions NXP added to its list of recent acquisitions with Athena SCS, a UK-based provider of embedded software and cryptography for smart cards and NFC. Lattice Semiconductor closed its all-cash $606.6 million acquisition of Silicon Image. Tools Cadence unveiled the Innovus Implementation System. The physical implementation tool sports massively parallel architect... » read more

Automotive Drives Novel IP Demands


In the past the automotive industry was a bit sleepy when it came to technologic innovations. Clearly, this is no longer the case. The automotive segment is now driving interesting capabilities and an unprecedented level of creativity by the IP and SoC engineering teams targeting this now-dynamic sector. Historically, electronics for automotive was very different from those aimed at consumer... » read more

Antennas Everywhere


A simple rule when it comes to electronics is that while digital circuits scale, antennas do not. That may not sound like a serious problem until you consider that as more devices get connected—cars, watches, industrial equipment—and they add more features that require interaction with the outside world, they need more antennas to make it all work. In the future, there literally will be... » read more

Modeling High-Performance Analog And RF Circuits In Nanometer-Scale CMOS


By Mick Tegethoff and David Lee Today’s consumer, communication, and computer electronic devices have clocks, communication interfaces, and high-speed signal-conditioning circuits that operate at radio frequencies (RF). Providing price-competitive products often requires monolithic integration of these circuits in low-power nanometer-scale bulk CMOS silicon. This is a worst-case scenario for... » read more

Rethinking The Cloud


Data center architectures have seen very few radical changes since the commercial introduction of the [getentity id="22306" comment="IBM"] System/360 mainframe in 1964. There have been incremental improvements in speed and throughput over the years, with a move to a client/server model in the 1990s, but from a high level this is still an environment where data is processed and stored centrally ... » read more

Veloce System-Level Power Analysis And Verification


Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of emulation platforms make them the ideal technology for system-level power analysis and verification. Veloce delivers unprecedented power verification and analysis capabilities. This paper shares ... » read more

The Week In Review: Design/IoT


Mergers & Acqusitions Mentor Graphics acquired Tanner EDA, bolstering their position in tools for analog, mixed-signal and MEMs. Terms of the deal were not disclosed. NXP joins forces with Freescale. The merger carries a $16.7 billion price tag and potentially creates a new leader in the automotive and MCU markets. Standards Accellera sent UVM 1.2 off to the IEEE P1800.2 working... » read more

AUTOSAR And FlexRay


This paper describes ways tools are quickly becoming the foundation for optimization processes that help engineers design profitable automotive products more efficiently than ever before. Standards are the enabling platform for the modern computer-based design tools that have transformed industries around the world. AUTOSAR is a leading effort to bring some standardization to the software platf... » read more

Blog Review: March 4


Is gate-level simulation still necessary? Mentor's Gordon Allan asserts it is, and gives a list of reasons why the pain is worth the peace of mind. Synopsys' Aron Pratt concludes his series on parameterization strategies with a process that allows the testbench to make use of parameterized interfaces without imposing limits on VIP access. Should you use EUV or quadruple patterning for 7nm... » read more

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