tag: Moore’s Law

The Future Of AI Is In Materials
By Sundeep Bajikar - 09 Jan, 2018 - Comments: 0

I had the pleasure of hosting an eye-opening presentation and Q&A with Dr. Jeff Welser of IBM at a recent Applied Materials technical event in San Francisco. Dr. Welser is Vice President and Director of IBM Research's Almaden lab in San Jose. He made the case that the future of hardware is AI. At Applied Materials we believe that advanced materials engineering holds the keys to unlocking... » read more

Mixed-Signal Issues Worse At 10/7nm
By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

Reflections On 2017: Manufacturing And Markets
By Brian Bailey - 28 Dec, 2017 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

Foundry Challenges in 2018
By Mark LaPedus - 27 Dec, 2017 - Comments: 6

The silicon foundry business is expected to see steady growth in 2018, but that growth will come with several challenges. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC are migrating from the 16nm/14nm to the 10nm/7nm logic nodes. Intel already has encountered some difficulties, as the chip giant recently pushed out the volume ramp of its new 10nm process from the second half ... » read more

Preparing For Bigger Changes Ahead
By Ed Sperling - 21 Dec, 2017 - Comments: 0

The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

What’s Next With Computing?
By Mark LaPedus - 18 Dec, 2017 - Comments: 1

At the recent IEDM conference, Jeff Welser, vice president and lab director at IBM Research Almaden, sat down to discuss artificial intelligence, machine learning, quantum computing and supercomputing with Semiconductor Engineering. Here are excerpts of that conversation. SE: Where is high-end computing going? Welser: We are seeing lots of different systems start to come up. First of all,... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 18 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

One-On-One: Mike Muller
By Ed Sperling - 30 Nov, 2017 - Comments: 0

Arm CTO Mike Muller sat down with Semiconductor Engineering to discuss a wide range of technology and market shifts, including the impact of machine learning, where new market opportunities will show up and how the semiconductor industry will need to change to embrace them. What follows are excerpts of that conversation. SE: It's getting to the point where instead of just developing chips, w... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy