The Next 5 Years Of Chip Technology

Experts at the Table, part 1: Scaling logic beyond 5nm; the future of DRAM, 3D NAND and new types of memory; the high cost of too many possible solutions.


Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments. The panel was organized by Coventor, a Lam Research Company. What follows are excerpts of that discussion.

L-R: Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt. Photo credit: Coventor, a Lam Research company.

SE: Looking beyond 10/7nm, is it going to be a straight line to 5nm and 3nm? Is it going to be more difficult than we expect? And is it even going to be possible?

Dougherty: It’s possible, and we’ve proven at multiple points in our history that it’s always possible, even if we don’t quite know how. We’ve always found a way through a variety of approaches, and I anticipate the same thing moving forward. I don’t anticipate it will be a straight line, though. It won’t be a hyperbola or an exponential line. We will get there, and there will be a variety of things the industry will uncover.

Gottscho: I agree. The path to 5nm is pretty clear. FinFETs will get extended at least to 5nm. It’s possible they will get extended to 3nm. And there will be some other solution after that, whether that’s gate-all-around horizontally or vertically. There will be new materials. There also will be a lot of challenges. We know how to fabricate fins that are 150nm tall with 5nm design rules. Fabricating them is one thing. Preventing them from collapsing is a different challenge. There are a lot of challenges, but I don’t have any doubts this industry will get there, and I don’t think it will be significantly delayed.

Shortt: About 30 years ago I first read an article explaining very clearly why we could never possibly make a device smaller than the wavelength of light using imaging. We all know how that turned out, and everyone who bet against optical lithography has been wrong. It always seems like you can’t project more than a couple generations out, but we always seem to be able to do it. As an inspection person, I’m astonished these devices are manufacturable. With 3D NAND, it’s astounding that we can make those.

Zhang: We are hearing from our customers on the supply side that scaling has not ended yet. In terms of lithography, we are driving that very hard with EUV at new nodes, with high-NA as an extension to that on the roadmap. So in terms of printing and patterning, we do have solutions out there. There is more of a challenge in how we manage the complexity and the cost. But we will get there.

Wolfling: I agree. Complexity is the key here. And the issue is really to work that in more than one way. There is room to extend finFETs. After that it will be nanosheets. Where will be the crossover? Will it be at 3nm or 2nm? At some point the industry crosses over. This is happening with EUV. It will happen with finFETs. The question is where it will happen.

SE: We have some big evolutionary problems to solve, though. There are interconnects, RC delay, and a bunch of issues that no one has ever been able to solve. Is this time different, particularly for logic, both from the manufacturing and from the measurement side?

Dougherty: The challenge that I see is actually the number of options. The technology we use to scale has expanded. If you go back several generations, you more or less knew the materials and basic structure you were going to use. Now, as you look ahead to 7nm and beyond, our supplier roadmaps say it could be any 1 of these 10 things. The answer is some combination of them, but there’s a lot more work that has to be done to screen down these various options at advanced nodes. We’re getting to the point where it may not be a single solution. For the longest time in this industry, everyone kind of aligned at the end of the day on the same solution. It’s possible there might be some divergence, like back-end-of-line metallurgy.

Zhang: The problem is not that you will hit the wall, but that you have many roads. The question is how we explore all of them. In the beginning they can be promising, but it’s difficult to say which one will be cost-effective and which one will be manufacturable. That’s part of the investment that is required—to investigate the different materials and the different directions. I don’t think the problem is that we’re facing a wall.

SE: No, but we are facing a lot of choices, right?

Gottscho: But with back-end-of-line, at least in the near term—it’s a couple generations out yet—there’s a real opportunity to lower the resistance just by getting rid of the barrier. That’s easy to say, not so easy to do. But when you look at the space occupied particularly vias, it’s dominated by highly resistant material that’s serving as a diffusion barrier. If we can solve that material problem, that will buy us a couple generations at the back-end of line. The contact resistance also is a huge problem, but that’s an example where people have been very creative with an architecture that uses wrap-around contacts, high-dose surface doping, and taking special care for interface properties. These problems are hard, and I don’t doubt there will be at least a couple different solutions. I am curious about metrology, though, because that is often a gate for process development.

Zhang: We were talking earlier about measuring something below an Angstrom. We are able to do that now in 3D. So metrology-wise, we do have solutions available. Whether we have solutions for everything we want to measure, that’s still a question.

Shortt: What I’ve seen over the years is that the length of time it takes for end-to-end cycle time, from concept to actually shipping, has gotten longer. What we find is that we need to start earlier. We have multiple generations leapfrogging each other, and multiple generations under development at any one time. We have a number of good ideas, but we have to start earlier thinking about them and doing the technical risk reduction to figure out what works and what doesn’t—and get rid of the stuff that doesn’t work and then keep going. So the full end-to-end cost is increasing for us for inspection and metrology. But with proper management, you do the technical risk reduction at the beginning, quickly throw away the ideas that don’t work, and then keep the ones that do.

SE: Another piece of logic involved in all of this is . We’ve already scaled up to 48 layers. Does this just keep scaling up, or are there physical limits here?

Gottscho: It keeps going up for awhile. I’m pretty optimistic about the future. I don’t think you can be in the semiconductor business and not be optimistic. We see a path to 256 layers. It’s going to be very challenging to go beyond that. But there are a lot of challenges to even get to 128 layers. Stress in the films is a big deal. If wafers come out looking like potato chips, that’s not good. And when you’re trying to stack one layer on top of another, that stress becomes a big problem in terms of distortion and overlay. One of the biggest problems is etching the memory holes. This is the most challenging etch I’ve seen in my 35 years in the etch business, with alternating layers of oxide and nitride, or oxide and poly, with aspect ratios approaching 100:1. But having said that, we have a solutions road map and we’re working on three generations of technology at the same time. It’s going to scale over the next 10 years.

Shortt: Do you see the future of 3D NAND doing that etch for 100 layers all in one step?

Gottscho: It will be a mixture. Our strategy is to push the etch technology to the highest aspect ratio that it will go, because we believe it’s in our customers’ interest to do as many layers as you can in one pass. But whether you stack 48 or 96 or 128, sooner or later you’re going to want to push out that choice of how many layers you’re going to stack as far as possible.

Wolfling: Once you start stacking, if you have three or four more generations and you stack four of them together, it’s not cost-effective. The more you can push the etching, the more you buy time for this direction.

SE: The other critical piece of the von Neumann architecture is DRAM. Can we go further with 1x technology to 1y, or do we need to move to some other technology such as phase change memory or STT-RAM?

Zhang: Our customers are marching down the path of 1x, 1y, 1z, and trying to squeeze out another nanometer. That’s been the case in the past couple years, and that will continue. As to how far we will go with that, we haven’t really seen another device on the horizon that will replace DRAM. We do see XPoint coming up as another viable memory solution that could be inserted into the current memory architecture. It will be interesting to see how that plays out versus DRAM.

Dougherty: But do you think it’s a matter of time with some alternative? There’s certainly a lot of work being done on all these different memories, though we don’t know what the intersection point is.

Zhang: That’s why folks are working on XPoint and other memories and seeing how far they can push that from a cost, performance and endurance standpoint. How that can match up to DRAM levels remains to be seen.

Shortt: We saw predictions at KLA-Tencor that 3D NAND would have taken over earlier, but with 3D NAND they were able to push that another generation or two beyond what a lot of people expected. That delayed the onset of 3D. The same will happen with DRAM. They’ll push it as far as they can.

Gottscho: I see a difference between DRAM and the 2D/3D NAND dynamic in the sense that 3D NAND was ready before 2D NAND ran out of gas. Right now it doesn’t appear as if there is a replacement for DRAM. Whether it’s STT-RAM or phase-change memory or resistive RAM, none of them can match the speed or endurance of DRAM. Necessity is the mother of invention, and we see at least two more generations after 1x. We are hearing about 1a. DRAM still has life in it, but it’s getting tougher. MRAM will probably come in as an embedded memory element in logic. It doesn’t look like a viable replacement for high-density DRAM.

Shortt: We’re also not seeing a lot of demand for yet for inspection of these new structures. You would think we’d see that early. We’ve seen a little bit, but not much.

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