Tech Talk: Moore’s Law

By Ed Sperling - 16 Mar, 2015 - Comments: 0

Aki Fujimara, CEO of D2S, talks with Semiconductor Engineering about the the technical challenges of scaling device and functionality, and the economics on cost per gate. [youtube vid=hBXtSCRbR64] » read more

One-To-Many: Shifting Left, Adding Gears

By Brian Bailey - 12 Mar, 2015 - Comments: 3

[getperson id="11034" comment="Aart de Geus"], chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], launched into high gear for his keynote talk at this year’s Design and Verification Conference (DVCon). The gathering attracted a record number of attendees, and it is estimated that about 350 people crammed into the room to listen to him talk about the shift left that is happening ... » read more

What Ford Is Driving

By Ed Sperling - 04 Mar, 2015 - Comments: 0

Jim Buczkowski, director of electrical and electronics systems research and advanced engineering at Ford Motor Co., sat down with Semiconductor Engineering to talk about quality, security, architectures, packaging and automotive's unique constraints. What follows are excerpts of that conversation. SE: As more electronic content is included in automobiles, what kinds of issues are you dealing... » read more

Partition Lines Growing Fuzzy

By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

One-On-One: Dave Hemker

By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

Back To The Future

By Ed Sperling - 02 Feb, 2015 - Comments: 0

The push to the next process node typically has meant that designs get simpler at existing and older nodes because the process technology is more mature and there have been so many chips developed at those nodes—many billions of them—that every possible corner case has been encountered hundreds, if not thousands, of times. That all makes sense in theory, but several key things have chang... » read more

Darker Silicon

By Katherine Derbyshire - 29 Jan, 2015 - Comments: 0

For the last several decades, integrated circuit manufacturers have focused their efforts on [getkc id="74" comment="Moore's Law"], increasing transistor density at constant cost. For much of that time, Dennard’s Law also held: As the dimensions of a device go down, so does power consumption. Smaller transistors ran faster, used less power, and cost less. As most readers already know, howe... » read more

Redefining Progress

By Ed Sperling - 22 Jan, 2015 - Comments: 0

After lots of wrangling over the whether Moore's Law is alive, dead, or languishing at somewhere in between, that discussion now seems about as relevant as the look and feel of Apple's early Macintosh operating system—an issue that back in the 1980s spawned a very public war with Microsoft. Today that argument is about as relevant as whether Betamax was better than VHS. Whether it's Moor... » read more

Manufacturing And Packaging Changes For 2015

By Brian Bailey - 22 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

IP Design Essentials For Reliability And SoC Integration

By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?