Redefining Progress

Time between process nodes is becoming far less relevant than solving the problems that crop up at new and existing nodes.

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After lots of wrangling over the whether Moore’s Law is alive, dead, or languishing at somewhere in between, that discussion now seems about as relevant as the look and feel of Apple’s early Macintosh operating system—an issue that back in the 1980s spawned a very public war with Microsoft. Today that argument is about as relevant as whether Betamax was better than VHS.

Whether it’s Moore’s Law, or some extrapolation of Moore’s Law, doesn’t really matter anymore. What does matter is that making SoCs is getting harder. In fact, it’s getting much harder. New chips are more complex because more functionality is being combined onto a single piece of silicon, or at least into the same package, to save on cost and energy. But that includes chips at established nodes as well as advanced nodes. With the emphasis on saving battery life, there are more power domains on all chips, which in turn leads to more clocks, more ways to shield wires that are turned on and off, and more analog components that are very susceptible to noise. There is more memory, too, which makes routing of signals much more difficult. And all of this creates timing closure issues for everyone, making design signoff a potentially career-limiting job.

It doesn’t get better with the Internet of Things, either. All the talk about IoT chips being simple to make because they’re being developed at older nodes was wishful thinking. Chips in smart watches are likely to rely on the most advanced processes and maybe even new architectures such as stacked die, because that will help save battery and shrink the form factor to something more streamlined and less clunky. No one wants to wear a box on his or her wrist. This is a market where form really does have to meet function, and it’s not going to happen with a 90nm process.

This leads to the real challenge, though, and one that goes back to why Moore’s Law is becoming less relevant. While most of the criticism has been in the time it takes for chip design on the front end, the reality is that it’s getting harder and taking longer to achieve significant yields on the back end. Until 28nm, process technology pretty much kept up with Moore’s Law. EDA tools, in contrast, have lagged. Yet with the push to multithreaded tools with SMP support, EDA is no longer the bottleneck. Even commercially available IP is relatively well characterized, given the information available for new nodes.

Now, for the first time in decades, the challenge is firmly on the manufacturing side. Being able to manufacture 3D transistors and memories with sufficient yield, and low enough defect density, to move process technology forward, is no longer a straight line. Even the tools to detect defects are being stretched beyond their limits. And despite the widespread dismissal of EUV, it will likely have a big opportunity for any process geometry beyond 22nm.

All of this takes time—more time to get new process nodes yielding sufficiently and with few enough defects to make it commercially viable. It’s no longer just about the time between nodes. It’s about the number and magnitude of the challenges at each new node, and how to solve them cost-effectively with the least amount of impact on wafers moving through fabs every hour. The problems are more difficult, and with more difficult problems come more difficult and much more complex formulas for success.

There is no law or observation that can adequately explain all of this. There are so many variables and tradeoffs that just comprehending all the pieces will likely require one or more very fast computers and some incredibly efficient algorithms. And even with all of that technology, it’s very likely that it will take longer to get each new process technology to a commercially viable state because the growing list of problems—particularly at the quantum level—aren’t necessarily the same from one node to the next. Welcome to the new world order.