RISC-V’s Software Portability Challenge

By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

Reducing SoC Power With NoCs And Caches

By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Data Routing In Heterogeneous Chip Designs

By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly

By Insaf Meliane - 29 Aug, 2024 - Comments: 0

Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or thousands of IP blocks, leading to significant design challenges. Multi-die architectures, which distribute functional blocks across multiple dice, demand expert planning to ensure connectivity and ... » read more

Chip Industry Week In Review

By The SE Staff - 16 Aug, 2024 - Comments: 0

The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications

By Ashley Stevens - 25 Jul, 2024 - Comments: 0

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Streamlining SoC Design With Advanced IP And Integration Solutions

By Andy Nightingale - 27 Jun, 2024 - Comments: 0

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The emphasis on physical awareness across solutions significantly reduces the iterative cycles of NoC placement and routing. By ensuring low latency and high efficiency, these advanced integration solution... » read more

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices

By Arteris - 27 Jun, 2024 - Comments: 0

Customer Overview Dream Chip Technologies is a German company that originated from a research think tank initiative comprised of private companies and government-funded organizations in the beginning of 1990. The results from this effort were foundational in establishing German mastery of microelectronics. Dream Chip Technologies started as a design services provider, developing intellectua... » read more

Turbocharging Cost-Conscious SoCs With Cache

By John Min - 30 May, 2024 - Comments: 0

Some design teams creating system-on-chip (SoC) devices are fortunate to work with the latest and greatest technology nodes coupled with a largely unconstrained budget for acquiring intellectual property (IP) blocks from trusted third-party vendors. However, many engineers are not so privileged. For every “spare no expense” project, there are a thousand “do the best you can with a limited... » read more

Cache Coherency In Heterogeneous Systems

By Ed Sperling - 01 Apr, 2024 - Comments: 0

Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?