tag: RTL

Manufacturing Test Robustness
By Kiran Vittal - 11 Sep, 2014 - Comments: 0

The recent 6.0 earthquake near Napa California caused close to $50 million in damages to the wineries and property in the region. The San Francisco bay area is accustomed to earthquakes and hence structural engineers design buildings to bear high intensity earthquakes amongst other natural disasters. The damage to property would have been much higher if not due to the strict guidelines followed... » read more

RTL Design-for-Power (DFP) Methodology
By Ansys - 10 Sep, 2014 - Comments: 0

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level tools are utilized as both design and verification tools, meaning that they help designers analyzing power and serve as the final ‘sign-off’ to ensure that power specifications are met. For standa... » read more

FinFET-Based Designs: Package Model Considerations
By Aveek Sarkar - 12 Jun, 2014 - Comments: 0

The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, tighter Vth control and higher drive strengths enable higher performance and increased integration while reducing overall energy consumption. But along with their advantages these devices introduce and... » read more

UPF-Friendly RTL
By Bernard Murphy - 13 Mar, 2014 - Comments: 0

On a recent customer visit, we were introduced to a new term – new to us at least – “UPF-friendly RTL”. While I hadn’t heard the term, I have been going on about the concept for some time – to the point, no doubt, of becoming terminally boring. We’ve had several customers quietly doing this for years, but now I’m starting to hear it from more customers, and from 1801 committee m... » read more

Clock Gating Optimization At RTL
By Various Writers - 12 Feb, 2014 - Comments: 0

In today’s semiconductor designs, lower power consumption is mandatory for mobile and hand-held applications for longer battery life and for networking or storage devices for low carbon footprint requirements. Clock power can consume as much as 60% to 70% of total chip power and is expected to increase further in the more advanced technology nodes. Hence, reducing clock power is very importan... » read more

How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs
By Various Writers - 15 Jan, 2014 - Comments: 0

Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines ... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Delicate Balance
By Joseph Hupcey III - 08 Aug, 2013 - Comments: 0

By Joe Hupcey III It’s not surprising that power optimization is a critical part of today’s complex designs. Unbeknownst to most consumers is an underlying methodology that every design engineer must follow to make sure a consumer device meets the power requirements of the consumer—even if the consumer doesn’t realize they’re demanding it. The situation in industrial products, suc... » read more

Watching And Waiting For DFP
By Ann Mutschler - 13 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Although the semiconductor industry has been talking about the need to optimize SoC designs for power for many years, it is safe to say it’s still in the very early stages of the 'Design for Power' approach. That’s not to say that methodologies and tools are not in place. There are actually a number of options available, depending on the level of abstractio... » read more

RTL Signoff
By Ed Sperling - 03 Jun, 2013 - Comments: 0

Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

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