tag: SOI

Wafer Leaders Extend Basis for Global SOI Supply
By Various Writers - 16 Oct, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation. SEH is a $12... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 08 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process inte... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 01 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are ... » read more

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE
;1-4 OCT, NAPA
By Various Writers - 25 Sep, 2012 - Comments: 0

The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the ... » read more

Materials, Architectures And Gordon Moore
By Ed Sperling - 21 Sep, 2012 - Comments: 0

Shrinking features on bulk CMOS using planar transistors has turned the semiconductor industry from a startup industry to one of the most efficient and robust industries in the world. Each new process node increases the number of chips that can be cut out of a single wafer, literally defining economies of scale. Gordon Moore defined the direction, which certainly created a long list of chall... » read more

Quiet, Steady And Sometimes Unexpected Advances For SOI
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Ed Sperling After years of talking about equivalent pricing, technical advantages and consistent processes, silicon on insulator finally appears to be making significant inroads—but not necessarily in ways, places, or even at process nodes where it initially was predicted to gain ground. What’s driving at least some of this change is the semiconductor industry’s progression toward ... » read more

Power And Performance: GSS Sees SOI Advantages For FinFETs
By Various Writers - 17 Sep, 2012 - Comments: 0

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI. To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s... » read more

Inflection Points
By Ed Sperling - 15 Aug, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem. [youtube vid=8ZhfJLkImlk] » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Dealing With Variability
By Barry Pangrle - 12 Jul, 2012 - Comments: 0

By Barry Pangrle Process, voltage and temperature, a.k.a. PVT, are well known to designers who are working to complete “signoff” for their designs. In order for a design to be production-ready, it’s necessary to ensure that the design is going to yield parts at a sufficiently high percentage for profitability and that it will still operate within the expected variation of the process and... » read more

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