Foundries Going Greener


The ongoing push towards green and energy-efficient systems is prompting the silicon foundries to jump on the bandwagon and devise their next-generation processes based on ultra-high voltage technology. For some time, several foundries have offered 1- and 0.5-micron, ultra-high voltage processes with ratings up to 800 volts. But seeking to get a jump for the next wave of designs, the special... » read more

Fabless-Foundry Model Under Stress


By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

FinFETs And 3D ICs


Semiconductor Manufacturing and Design talks with Soitec's Steve Longoria about the role of FD-SOI in advanced semiconductor design and 3D stacks. [youtube vid=P7Ld14s9NY4] » read more

Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET


The following is a special guest post by Steve Longoria, Senior VP of Worldwide Business Development at Soitec.  It first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization. ~~ Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to th... » read more

Crunch Time


Never have so many things conspired to make design so difficult—at least not at the same time. At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at leas... » read more

Off The Planar


By Pallab Chatterjee 3D devices, FinFETs and new memory technologies are not just a future direction anymore. They’re real. That became evident at this year’s IEDM conference, where the focus of a number of sessions was on modeling, failure and reliability models, as well as lower power supply operations for these devices. Because FinFETs are not standard 2D MOS devices, their use i... » read more

Executive Briefing: The End Of CMOS?


Steve Longoria, senior vice president of Soitec, talks with System-Level Design about why silicon on insulator has suddenly become essential to semiconductor manufacturing and what it will mean for Moore's Law. [youtube vid=kNl1RSEpqKc] » read more

SOI Conference Shows SOI Driving Key Roadmaps


By Adele Hars The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at th... » read more

Ultra-thin wafers for 450mm FD-SOI on schedule


While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready? Engineered substrates like SOI wafers need to ... » read more

Does SOI matter to the designers using the chips?


By Adele Hars Much of the SOI vs. bulk discussion zeros right in on the manufacturing bottom line:  which is cheaper?   And absolutely, customers want the most cost-effective solution.  But the best of all possible worlds is if you can save them money and give them all the bells and whistles they're looking for, too, right? [caption id="attachment_150" align="alignleft" width="150" capti... » read more

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