How Reliable Is Your IP?


Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Powerful Memories


Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

MRAM Begins To Attract Attention


By Mark LaPedus In the 1980s, there were two separate innovations that changed the landscape in a pair of related fields—nonvolatile memory and storage. In one effort, Toshiba invented the flash memory, thereby leading to NAND and NOR devices. On another front, physicists discovered the giant magnetoresistance (GMR) effect, a technology that forms the basis of hard disk drives, magnetores... » read more

Memory Gets Smarter


By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

VLSI Kyoto – The SOI Papers


By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

Scaling The Lowly SRAM


By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Thanks For The Memories


By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Universal Memories Fall Back To Earth


By Mark LaPedus Ten years ago, Intel Corp. declared that flash memory would stop scaling at 65nm, prompting the need for a new replacement technology. Thinking the end was near for flash, a number of companies began to develop various next-generation memory types, such as 3D chips, FeRAM, MRAM, phase-change memory (PCM), and ReRAM. Many of these technologies were originally billed as “uni... » read more

Soft Errors Create Tough Problems


By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

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