Navigating Heat In Advanced Packaging


The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Blog Review: Jan. 17


Cadence's Rajneesh Chauhan introduces the Back-Invalidate feature in Compute Express Link (CXL) 3.0 and how it contributes to the efficient functioning of modern data center architectures by upholding cache coherence across multiple hosts and devices. Synopsys' Brett Murdock and Dana Neustadter point out the importance of protecting against DRAM attacks such as Rowhammer, RAMbleed, and cold-... » read more

Which Data Works Best For Voltage Droop Simulation


Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Renesas will acquire Transphorm, which designs and manufactures gallium nitride power devices, for about $339 million. GaN, which is a wide-bandgap technology, is used for high-voltage applications in a slew of markets, including EVs and EV fast chargers, as well as data centers and industrial applications. Cadence acquired Invecas, a provider o... » read more

Glitch Power Issues Grow At Advanced Nodes


An estimated 20% to 40% of total power is being wasted due to glitch in some of the most advanced and complex chip designs, and at this point there is no single best approach for how and when to address it, and mixed information about how effective those solutions can be. Glitch power is not a new phenomenon. DSP architects and design engineers are well-versed in the power wasted by long, sl... » read more

Getting Optimal PPA For HPC & AI Applications With Foundation IP


By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

Blog Review: Jan. 10


Keysight’s Jenn Mullen explains how ChatGPT’s tools can help quality assurance (QA) engineers and software testers overcome test automation debt, and become more productive and able to deliver consistently high-quality products to market faster. Siemens’ Keith Felton discusses how the paradigm of “shift-left” power delivery analysis has emerged as a critical methodology in addressi... » read more

Pressure Builds On Failure Analysis Labs


Failure analysis labs are becoming more fab-like, offering higher accuracy in locating failures and accelerating time-to-market of new devices. These labs historically have been used for deconstructing devices that failed during field use, known as return material authorizations (RMAs), but their role is expanding. They now are becoming instrumental in achieving first silicon and ramping yie... » read more

SLM Analytics Of In-Chip Monitor Data Unlock Greater Productivity And Cost Savings


When it comes to measuring key operational metrics such as power and performance of your silicon, in-chip monitors have been the longstanding cornerstone for providing such valuable measurements and insights. Data captured from these monitors – process monitors configured in the form of ring oscillator chains being the most common – can tell you if your chip is meeting the requisite power o... » read more

Chip Industry Week In Review


By Susan Rambo, Jesse Allen, and Liz Allan The U.S. government will provide about $162 million in federal incentives, under the CHIPS and Science Act, to help Microchip onshore its semiconductor supply chain. The move is aimed at securing a reliable domestic supply of MCUs and mature-node chips. “Today’s announcement will help propel semiconductor manufacturing projects in Colorado and O... » read more

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