Best Options For Using AI In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Complex Mix Of Processors At The Edge


With AI changing so fast, it’s a juggle for companies to ensure they can deliver the best performance now while also future-proofing for unknown AI models or a completely different approach to training and inference that may emerge. There are a slew of options for high-end and budget phones, hyperscalers, and low-cost, low-power edge devices, and while GPUs keep making headlines, many designe... » read more

Chip Industry Week in Review


Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story."  Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

System-Level Design For 1.6 Tbps Interoperability In AI Data Centers


By Madhumita Sanyal and Diwakar Kumaraswamy The rapid escalation of AI/ML workloads—driven by increasingly large language models—is reshaping high-performance computing and AI data center architectures. Real-time inference and large-scale training are pushing the limits of compute and interconnect performance. With model sizes and parameter counts doubling every 4–6 months, infrastruct... » read more

Re-Architecting AI For Power


The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

Reliable Training Data Paramount To AI Model Success


AI systems are increasingly being integrated into safety- and mission-critical applications ranging from automotive to health care and industrial IoT, stepping up the need for training data that is reliable, secure, and which is generated from trusted sources. AI activity is growing exponentially, as everybody tries to figure out how to apply it to their domain, application, or workload. In ... » read more

Building An AI Chip: Pre Silicon Planning


This white paper highlights the challenges of AI chip design, including balancing performance, cost, and power efficiency. It emphasizes the importance of early architecture exploration to avoid costly design revisions and ensure optimal power-performance trade-offs. The paper underscores the need for secure, efficient, and scalable IP solutions to meet the evolving demands of AI applications, ... » read more

Best Practices to Optimize Infrastructure for Simulations


Our Best Practices Guide equips you with expert strategies for leveraging high-performance computing (HPC) to maximize Ansys workload efficiency and overcome common challenges. As simulation complexity increases, a robust computing infrastructure is essential for rapid and large-scale modeling. Modern HPC systems provide: High-core-count CPUs for superior memory and compute perfo... » read more

Transforming Test For Co-packaged Optics


Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day. To enable this change in production manufacturi... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding


As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

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