3D NAND Race Faces Huge Tech And Cost Challenges

By Mark LaPedus - 23 May, 2019 - Comments: 8

Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Micron, Samsung, SK Hynix and the Toshiba-Western Digital duo are developing 3D NAND products at the next nodes on the roadmap, but the status of two others, Intel and China’s Yangtze Memory Technologies Co. (YMTC), is les... » read more

Lithography Challenges For Fan-out

By Mark LaPedus - 12 Feb, 2019 - Comments: 3

Higher density fan-out packages are moving toward more complex structures with finer routing layers, all of which requires more capable lithography equipment and other tools. The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these critical dimensions (CDs), fan-outs will provide better per... » read more

Packaging Biz Faces Challenges in 2019

By Mark LaPedus - 10 Dec, 2018 - Comments: 0

The IC packaging industry is bracing for slower growth, if not uncertainty, in 2019, even though advanced packaging remains a bright spot in the market. Generally, IC packaging houses saw strong demand in the first part of 2018, but the market cooled in the second half of the year due to a slowdown in memory. Going forward, the slower IC packaging market is expected to extend into the first ... » read more

Cost Analysis of a Wet Etch TSV Reveal Process

By Veeco - 10 Dec, 2018 - Comments: 0

Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today. TSVs offer distinct benefits in form factor and improved performance and can enable new, innovative designs not previously possible. To scale this valuable technology and spark industry adoption, there is a need to refine and optimize the TSV reveal process to red... » read more

Finding New Dimensions Of Innovation

By Gary Dagastine - 15 Nov, 2018 - Comments: 0

Whenever a company announces a major strategy shift and restructuring, such as pivoting away from 7nm FinFET technology development, it’s understandable that confusion, uncertainty and misunderstandings may arise. The best way to allay these concerns is to take an objective look at the situation: Demand for chips for the automotive, IoT, mobility and data center/wireless infrastructure mar... » read more

Defect Challenges Growing In Advanced Packaging

By Mark LaPedus - 08 Oct, 2018 - Comments: 0

The current defect inspection systems for packaging are running out of steam for the latest advanced packages, prompting the need for new tools in the market. In response, several vendors are rolling out new defect inspection systems for use in various advanced packages, such as 2.5D/3D technologies and fan-out. The new defect inspection systems are more capable than the previous tools, but ... » read more

Return Of The Organic Interposer

By Ed Sperling - 06 Aug, 2018 - Comments: 2

Organic interposers are resurfacing as an option in advanced packaging, several years after they were first proposed as a means of reducing costs in 2.5D multi-die configurations. There are several reasons why there is a renewed interest in this technology: More companies are pushing up against the limits of Moore's Law, where the cost of continuing to shrinking features is exorbitant. ... » read more

Practical Methods To Overcome The Challenges Of 3D Logic Design

By Benjamin Vincent - 25 Jun, 2018 - Comments: 0

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other. The Challenge: How can we shrink logic devices? Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together... » read more

The Case For Chiplets

By Ed Sperling - 07 May, 2018 - Comments: 4

Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

Architecture, Materials And Software

By Ed Sperling - 12 Apr, 2018 - Comments: 0

AI, machine learning and autonomous vehicles will require massive improvements in performance, at the same power consumption level (or better), over today's chips. But it's obvious that the usual approach of shrinking features to improve power/performance isn't going to be sufficient. Scaling will certainly help, particularly on the logic side. More transistors are needed to process a huge i... » read more

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