Lithography Challenges For Fan-out

Advanced packaging moves into high-volume mobile markets, but requires more sophisticated equipment and lower-cost processes.


Higher density fan-out packages are moving toward more complex structures with finer routing layers, all of which requires more capable lithography equipment and other tools.

The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these critical dimensions (CDs), fan-outs will provide better performance, but there are several manufacturing and cost challenges to reach and break the 1µm barrier. Moreover, at this point only a few customers require these high-end packages.

Nevertheless, fan-out packaging is gaining steam in high-volume markets. “Mobile continues to be one main growth driver for both low-density and high-density fan-out,” said John Hunt, senior director of engineering for ASE. “Automotive will start to pick up momentum, as we get fan-out qualified for grade 1 and 2. And server applications are seeing growth for the high-end market.”

A key part of a fan-out is the redistribution layer (RDL). RDLs are the copper metal connection lines or routing layers that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal line.

Fig. 1: Redistribution layers. Source: Lam Research

From there, fan-out is split into two segments—low-density and high-density. Low-density fan-out consists of RDLs with greater than 8μm line/space (8-8μm). Used in servers and smartphones, high-density fan-out has multiple layers of RDLs in a package, with CDs at 8-8μm and below. Generally, 5-5µm is the mainstream high-density technology, with 1-1µm and below in the works.

“There is still a wide range of fan-out type of technologies in terms of how aggressive they are regarding the design rules. A lot of it is dominated by form factor, what you want for performance, and what you can tolerate for cost,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “Redistribution layers with smaller critical dimensions enable reducing the total number of redistribution process levels in a fan-out package. This in turn reduces the total packaging cost and improves yield.”

Cost is a factor on several fronts. Not all need high-density fan-out. Fan-out with aggressive CDs are relatively expensive and limited to high-end customers. The good news is that there is a plethora of other and lower cost packaging options besides high-density fan-out.

Then, on another front, customers are pushing the packaging houses to reduce their manufacturing costs, especially for fan-out and other advanced packages. In fan-out, there are several process steps, including lithography, the art of patterning features on structures.

In packaging, there are several different lithography tool types, such as aligners, direct imaging, laser ablation and steppers. Each technology is different with various capabilities. All told, packaging houses will likely use different tool types for fan-out.

What is fan-out?
Fan-out packaging is a hot market. In fan-out, the dies are packaged while on a wafer. Fan-out doesn’t require an interposer, making it less expensive than 2.5D/3D.

There are three types of fan-out packages—chip-first/face-down; chip-first/face-up; and chip-last or RDL first.

In the chip-first/face-down flow, the chips are first processed on a wafer in the fab. The wafer is moved to a packaging house, where the chips are diced. Then, using a die attach system, the dies are placed on a temporary carrier.

An epoxy mold compound is molded over the dies and carrier, forming what’s called a reconstituted wafer. Then, the RDLs are formed within the round reconstituted wafer.

In a simple RDL flow, a copper seed layer is deposited on the substrate. A photoresist is applied on the structure and then patterned using a lithography tool. Finally, an electroplating system deposits the copper metallization within the package, forming the final RDLs.

The RDL CDs depend on the application. Many fan-out packages don’t require advanced RDLs. Packages at 5-5µm and above will remain the mainstream technologies for the foreseeable future. Then, at the high end, ASE is moving toward RDLs at or near 1-1μm. Meanwhile, TSMC is developing fan-out at 0.8μm with 0.4μm in R&D. Eventually, high-end fan-out will support high-bandwidth memory (HBM).

“There are different approaches of doing fan-out. We see a trend where the CDs are getting smaller and more challenging. Copper pillar pitch is also getting smaller,” said Y.C. Wong, general manager of Veeco’s Litho System Asia business unit. “Typically, for mainstream, the RDLs are still 5-5μm and above in production. We are seeing some small volume at 2-2μm or 3-3μm. 1-1μm is just engineering tape-out right now. All of this will be driven when 5G takes off and when memory bandwidth demand becomes higher. That will drive more demand for 2-2μm and 3-3μm and below.”

Nonetheless, there are several challenges with all fan-out. “The main challenge with fan-out is the warpage/wafer bow. In addition, die placing can also impact wafer flatness and stress on the dies. Then, die shift induces challenges for the lithography steps and alignments,” said Amandine Pizzagalli, an analyst at Yole Développement.

Cost is also key. Packages with aggressive CDs tend to be more expensive. On the flip side, packages with more relaxed CDs are less expensive. In either case, customers are price sensitive when it comes to IC packaging. They want to reduce their packaging costs as much as possible. So, they want the packaging houses to drive down their manufacturing costs.

There is another side to the story. A packaging customer may want a fan-out product with aggressive RDLs. But the package must achieve a certain volume to justify the R&D. If the package can’t meet a volume target, it’s difficult to get a return. And so, there may not be an incentive to move to a package with smaller RDLs.

Aligners to steppers
To be sure, lithography plays a key role in fan-out and other packaging types. It is also critical in the fab, where lithography equipment is used to pattern features at the nanoscale. Meanwhile, in packaging, lithography and other tools are used to process bumps, copper pillars, RDLs and through-silicon vias (TSVs). These structures are measured at the μm level.

In total, the lithography equipment market for packaging is expected to reach $141.6 million in 2019, up from $128.7 million in 2018, according to Yole Développement. Some 85% of all new equipment purchases involve steppers, followed by mask aligners with less than 15%, according to Pizzagalli.

Aligners and steppers fall into a category called photolithography or optical lithography. For this, the process starts with a photomask. A designer designs an IC or a package, which is then translated into a file format. Then, a photomask is developed based on that format.

The photomask is a master template for a given design. After a mask is developed, it is shipped to the fab or packaging house. The mask is placed in a lithography tool. The tool projects light through the mask, which patterns the images on a device.

For years, mask aligners were the mainstream lithography tool for packaging. “Mask aligners work by directing the projection of a full-area photomask to a substrate. Due to the fact that there is no reduction of projection optics, the mask has to be placed in close proximity to the wafers. Hence, the resolution is limited to about 3µm line/space for production applications,” said Thomas Uhrmann, director of business development at EV Group.

Today, mask aligners are used for packages, MEMS, and LEDs. “While line/space requirements below 3µm are tough to reach in production, mask aligners have other benefits in advanced packaging. For example, mask aligners have performance and cost advantages in the areas of bumping and thick resist exposure where high intensities and high exposure times are needed,” Uhrmann said.

For more advanced applications, though, the industry has migrated to a lithographic system called a stepper. Using advanced projection optics, steppers have higher resolutions than aligners.

A stepper transfers the image of a feature from a mask onto a small portion of a wafer. The process is repeated until the wafer is processed. Canon, Rudolph, Veeco and others compete in the stepper market for packaging.

For many apps, packaging houses moved to steppers for several reasons. “When we started to look at what the stepper could do, we could offer some dramatic improvements,” Veeco’s Flack said. “Decreasing CDs have been a big consideration in the last few years. It’s tightening the overlay to match the CDs. And now, there’s a much wider range of substrates that you must be able to handle.”

Meanwhile, in the fab, chipmakers use 193nm wavelength lithography systems to print tiny features. In packaging, though, the feature sizes are larger, so packaging houses don’t require tools at these wavelengths. Instead, they use lithographic equipment at longer wavelengths, namely 436nm (g-line), 405nm (h-line) and 365nm (i-line).

In packaging, some steppers are i-line only, while others support more wavelengths. For example, Veeco sells what it calls a broadband stepper, which supports all three wavelengths–436nm, 405nm and 365nm. These are produced by a broadband spectrum mercury light.

Fig. 2: Inside Veeco’s stepper. Source: Veeco

For more aggressive CDs, this stepper can be tuned to support an “i-line only” mode, enabling features down to 1-1μm. Additionally, the tool can support a “ghi” mode, enabling features above 2-2μm.

Steppers are used to produce a range of IC packages, including fan-out. In fan-out, lithography tools help form the RDLs.

These systems must also deal with die shift. As stated, when the dies are embedded in a reconstituted wafer, they tend to move during the flow, causing an unwanted effect called die shift. This impacts the yield.

In response, the industry is developing lithography tools with better alignment techniques to compensate for die shift. “There are two ways you can address it. From a lithographic standpoint, you can correct it as much as you can. You can adjust the scales across the wafer. You can adjust the magnification. But that assumes everything shifts the same way. If the shifts are random, then it’s almost impossible to correct that way,” Veeco’s Flack said. “For higher end applications, people will work hard to make sure the die doesn’t shift. That can be done by the technique of placing the die and aligning the die in some cases.”

Die shift remains an ongoing challenge in all fan-out. Another challenge is to produce the RDLs. With little or no trouble, the industry is making fan-out with RDLs at 5-5μm. Even 2-2μm is in production.

The challenges grow as fan-out moves to 1-1μm and beyond. The trick is to produce fine RDLs with good yield.

The industry is capable of 1-1μm. For example, using an i-line only mode in a stepper, Veeco has demonstrated resolutions at 1-1μm. The stepper has a variable numerical aperture (NA) lens and 1X reticle.

There are some challenges. During the RDL process, the copper thickness must be maximized to lower the resistance of the metal lines, according to a recent paper from Veeco and Imec. So, the aspect ratio of the photoresist must be maximized. This, in turn, requires lithography tools with a large depth of focus to handle the height variations in fan-out, according to the paper.

Meanwhile, others offer i-line only systems. For example, Canon’s latest i-line tool features a 0.24 NA lens, enabling resolutions at ≤0.8μm.

“Leading-edge 1µm advanced packaging processes require the use of chemically amplified resists that are only sensitive to i-line wavelengths due to their photo acid generator properties. So it requires i-line exposure light to realize less than 1µm resolution,” said Doug Shelton, marketing manager at Canon. “Customers requesting wide-band exposure will be targeting rough pattern layers using mature DNQ resists that have sensitivity to i-line and h-line resists, not g-line. For these less challenging applications, we can prepare a system with an option to allow wide-band i/h-line exposure to boost throughput for rough processes.”

So, it’s certainly possible to push the RDLs beyond 1µm using today’s technologies, but that remains unclear. It’s a subject for debate in the packaging industry. Regardless of the stepper type, though, there are several challenges in going beyond 1-1μm. The lithography tools are certainly capable, but there are other issues regarding the current RDL flow.

“When you get down below 1-1μm, you start to have other issues that are not lithography related, which will limit the speed of adoption,” Veeco’s Flack said. “As long as the seed layer is a small percentage of the width of the copper line, it works great. When you get down to less than 1μm, the seed layer is a significant percentage of the linewidth. As a result, you start to have yield problems.”

Simply put, the traditional RDL process poses as a potential roadblock moving beyond 1-1μm. “It will be a real challenge for the industry with the transition at that point,” Flack said.

So the industry is looking at other process flows, namely dual damascene. For years, chipmakers have used a damascene process to make the copper interconnects in chips in the backend-of-the-line (BEOL) in a wafer fab.

In dual damascene, the process steps are similar for both the BEOL and packaging. In packaging, an insulating layer is deposited on the device. Then, a trench is patterned and etched and the trench is filled with copper.

For packaging, the damascene flow works, and it’s possible to push the RDLs beyond 1-1μm. “It works great, but it’s just expensive. There’s a technical solution, but it may not be a cost-effective solution,” Flack said.

TSMC is exploring the damascene process, but it may be too costly for most. So the industry needs a cost-effective breakthrough in the arena.

Laser imaging, ablation and others
Laser direct imaging is another lithographic technique for packaging. Laser imaging is like direct-write or maskless lithography. It directly writes features on a die without a mask, thereby reducing the cost in packaging.

Orbotech and Screen sell laser direct imaging systems. Deca Technologies also has developed a proprietary laser direct technology.

Laser imaging could solve the die shift issues in fan-out. As stated, the first step is to make a reconstituted wafer. Then, dies are placed on the wafer using a die attach system.

“The problem occurs here. When you put the chips on, the chips are not perfect with respect to each other. It’s very difficult to keep the chips exactly where we want them within a few microns,” said Tim Olson, chief technology officer of Deca.

That’s where Deca’s Adaptive Patterning technology fits. ASE, an investor in Deca, is producing the M-Series fan-out products based on this patterning technique.

Fig 3: M-Series vs. traditional eWLB fan-out Source: ASE

Deca’s technology consists of a process flow with four modules—wafer prep, panelization, fan-out, and finishing. It enables fan-out packages with multiple layers at 5-5μm with finer RDLs in R&D.

In wafer prep, you plate copper features on the die. Then, in the panelization step, the dies are placed in a reconstituted wafer using a high-speed system at a rate of 28,000 chips per hour. In comparison, a traditional die-attach system operates at 2,000 chips or more an hour.

From there, the actual position of every die is measured on the wafer using an inspection technique. “Die measurement inspection is performed as the last step in the panelization process and is used in the real-time design for each panel in manufacturing,” Olson explained.

Then, the RDLs are developed in a chip-first, die-up flow. During the exposure step, the system recalculates the RDL pattern to accommodate every die shift in every wafer. This takes 28 seconds. The overall throughput is 120 wafers an hour.

“Adaptive Patterning is a system designed to automatically compensate for natural variation in manufacturing rather than focusing on elimination of all variation,” Olson said. “In a typical application, devices are allowed to vary by up to 60μm in ‘X’ and ‘Y’ through chip attach, molding and other process steps. Adaptive Patterning removes 97% of the variation automatically through real-time design in manufacturing, enabling effective interconnect tolerances below 2μm. The next generation of Adaptive Patterning in development will support 2μm features, with a scaling roadmap to 0.8μm.”

Then, using the same technology from Deca, ASE plans to ramp up panel-level fan-out in 2019 or 2020. ASE’s panel-level fan-out will also use Adaptive Patterning.

Meanwhile, Suss MicroTec is developing a dry patterning technology called laser ablation. Suss’ excimer ablation stepper combines ablation with mask-based patterning. It is capable of 3μm line/space with 2-2μm in the works.

“Excimer laser ablation is the direct removal of material using the characteristics of high power UV excimer laser sources. Typical wavelengths are 308nm, 248nm and 193nm,” said Markus Arendt, president and general manager of photonic systems at Suss. “Excimer ablation instantaneously transforms the compatible target material (i.e. polymers, organic dielectrics) from solid phase to gas phase and byproducts (i.e. sub-micron dry carbon particles), resulting in little to no heat affected zone and much less debris.”

With the tool, Suss is focusing is on wafer-level processes. In addition, it has developed a dual damascene RDL flow with other technologies in R&D.

“The product roadmap includes many new items,” Arendt said. “However, the two most notable ones are: 1) a new large field, high-NA projection lens to achieve 2μm L/S in production, and 2) a dual-laser version to allow for a larger scan beam to significantly increase throughput and reduce cost-of-ownership.”

Brewer Science, meanwhile, is working on another approach. It uses a thin film in a mold compound that works like a stencil, which addresses die shift. “It’s a replacement for epoxy mold compound,” said Rama Puligadda, Brewer’s executive director of advanced technologies. “You pre-form a stencil where you want to make cavities in silicon.”

Clearly, there is no shortage of innovative lithographic solutions for packaging. But it will take some breakthroughs to go well beyond 1-1μm. Even if the industry figures it out, it must meet a cost spec for demanding customers. Those factors will keep the industry busy for some time.

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Marc-David Levenson says:

Deja -vue all over again!
What ever happened to all the PerkinElmer (Silicon Valley Group) 300 and 500 full-wafer scanners? Could that technology make a come-back?

Priya Mukundhan says:

Great summary! Is it possible to add more details to the comment about Cu seed layer (thickness being significant perentage at 1um RDL and below) and its impact to yield? How is this currently being measured or monitored? Thanks

Ludo Vandenberk says:

Why not introducing UV curing (stabilize resist)?

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