tag: test

ATE Platform Strategy Gains Ground
By Kenji Tsuda - 10 Feb, 2014 - Comments: 0

More than a decade ago, at the urging of Intel, the ATE industry set out to reduce the cost of test in the digital chip market. Backed by companies such as Intel, Motorola, Renesas, Advantest and others, they formed an ATE consortium to make this all work. The aim of the consortium was to devise an "open architecture" for ATE. This would enable the development of third-party plug-and-play m... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 12 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As more pieces are integrated into complex SoCs... » read more

A Guide To Power-Aware Memory Repair
By Various Writers - 04 Dec, 2013 - Comments: 0

The number of embedded memories contained within an SoC continues to grow rapidly. This growth has driven the need for rethinking manufacturing test strategies as embedded memories represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must incorporate some form of repair methodology in o... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

The Week In Review: Sept. 16
By Mark LaPedus - 16 Sep, 2013 - Comments: 0

By Mark LaPedus In June, Crucial.com teamed up with Lou Ferrigno to invite all frustrated computer users to submit a short video showing their most fearsome, frustration-filled and computer-induced roar. Each video was evaluated according to a variety of factors, including volume, enthusiasm, perceived distress, frustration, anxiety, irritation and overall hopelessness. The memory module suppl... » read more

The Week In Review: Sept. 13
By Ed Sperling - 13 Sep, 2013 - Comments: 0

By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

ATE Market Changes With The Times
By Jeff Chappell - 15 Aug, 2013 - Comments: 0

By Jeff Chappell A declining PC market in recent years coupled with the continuing growth of mobile phones and tablets has meant changes throughout the semiconductor supply chain, and automated test equipment is no exception. For example, a decade ago memory test—namely DRAM—was a large market compared with that of nascent system-on-a-chip (SoC) testing. In fact, at the time some test e... » read more

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